Oscillators – Automatic frequency stabilization using a phase or frequency... – Tuning compensation
Reexamination Certificate
2000-05-04
2001-09-11
Grimm, Siegfried H. (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Tuning compensation
C331S025000
Reexamination Certificate
active
06288614
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a phase-locked loop for generating an output signal which has a predetermined frequency and a locked phase relative to a reference signal of a predetermined reference frequency. The invention relates to a phase-locked loop enabling to increase the cut-off frequency or the low pass filter and the resolution of the phase/frequency discriminator, in particular for a low meantime interval error (MTIE), a low phase-jitter even at low frequencies and a fast tracking speed and a minimum time for locking to the reference frequency.
BACKGROUND OF THE INVENTION
The phase-locked loop (PLL) is a useful building block available from several manufacturers as a single integrated circuit. A phase-locked loop PLL typically contains a phase detector PFD, an amplifier A
V
, a low pass filter LPF (both contained in a low pass filter means LPFM) and a voltage-control oscillator VCO as is schematically shown in
FIG. 1
a.
In a phase-locked loop a mixture of digital and analogue techniques are combined in one package. The phase-locked loop finds broad applications in tone decoding, demodulation of AM and FM signals, frequency multiplication, frequency synthesis, pulse synchronization of signals from noisy sources, e.g. magnetic tape, and regeneration of “clean” signals.
The basic operation of the phase-locked loop is as follows. The phase detector PFD is a device that compares two input frequencies, i.e. the predetermined frequency f
2
of an output signal from the voltage controlled oscillator and a predetermined reference frequency f
1
of a reference signal f
1
. The phase detector generates an output that is a measure of the phase difference between the two signals f
1
, f
2
(if, for example, they differ in frequency, it gives a periodic output at the difference frequency). If f
1
is not equal to f
2
the phase deviation signals, after being filtered and amplified in the low pass filter means LPFM, causes the voltage-controlled oscillator frequency to deviate in the direction of f
1
. If the operating conditions are correctly set, the voltage-controlled oscillator will quickly “lock” its output frequency f
2
to the reference frequency f
1
, maintaining a fixed phase relationship with the input signal.
The generated control voltage input to the VCO is a measure of the output frequency f
2
. The VCO output is a locally generated frequency, in the simplest case equal to f
1
thus providing a clean replica of f
1
, which may itself be noisy. The wave forms of f
1
, f
2
are not restricted to any particular waveform, i.e. the VCO output signal can be a triangle wave, sign wave or any other wave. Therefore, the phase locked loop PLL provides an easy technique, for example to generate a sign wave locked to a train of input pulses.
Since the phase detector PFD compares the phase (or the frequency) of the reference frequency f
1
with the predetermined frequency f
2
output by the voltage controlled oscillator the phase deviation signal S is a signal which—dependent on the tracking behavior of the phase-locked loop PLL—assumes values according to the phase/frequency deviation between f
1
and f
2
.
STATE OF THE ART
To allow a more flexible design of the afore mentioned parameters and to allow a generation of output frequencies f
2
at a multiple of the reference frequency f
1
and also to improve on the afore mentioned parameters, it is conventional practice to provide dividers for dividing the predetermined frequency f
2
and the reference frequency f
1
by respective frequency division factors p, q in two dividers DIV
1
, DIV
2
provided in front of the phase detection means PFD as is illustrated in
FIG. 1
b.
FIG. 1
b
shows features of as known from U.S. Pat. No. 5,256,980. In this document, as
FIG. 1
b,
two frequency dividers are provided, whereby each of them has particular division factors m, m+1, m−1 and n, n−1, n+1. The purpose in this prior art document is to keep the rising edges of the two clock signals in time alignment. That is, the nominal values n, m are only changed by ±1 in order to keep the rising edges in time alignment. This switching of ±1 allows to finally adjust the phase of the synthesizer output and/or its frequency.
In
FIG. 1
b,
with an appropriate selection of the frequency division factors p, q, the phase detection means PFD compares divided frequencies f
1
/p and f
2
/q to obtain the phase deviation signal S. There are also realizations where only one divider DIV
1
is used. It is clear from
FIG. 1
b
that with the appropriate selection of p, q together with an appropriate selection of the cut-off frequency and the filter characteristic of the low pass filter LPF and the amplification A
v
, the tracking speed, the locking speed, the MTIE (meantime interval error) as well as the phase-jitter can be influenced. Having divided the frequencies f
1
, f
2
by appropriate frequency factors p, q desired frequency ratios can be adjusted.
The output of the phase detector PFD (which can e.g. be a mixer or a flip-flop), i.e. the phase deviation signal S, comprises a spectrum containing the control information in a lower frequency region thereof. To extract this control information, the spectrum is low pass-filtered by the low pass filter LPF having a cut-off frequency given by the particular application. When a large number of phase comparisons is performed in a given time, i.e. when the frequencies f
1
/p, f
2
/q are large, then the spectrum is quite broad, the cut-off frequency of the low pass filter LPF can be quite large and it is sufficient to use a low pass filter of a comparatively simple configuration (6 dB/decade), since the higher spectral components are far away from the application dependent low pass filter cut-off frequency. By contrast, when over a given period of time only a small number of phase comparisons can be performed, i.e. when the frequencies f
1
/p, f
2
/q are comparatively small, then the spectrum is rather narrow and it is necessary to select a low cut-off frequency of the low pass filter LPF and to use low pass filters of a rather complicated design. (e.g. 30 to 40 dB/decade), since the higher spectral components are rather closely located to the application dependent low pass filter frequency.
Depending on the cut-off frequency and the selected filter design, the output of the low pass filter means LPFM may still contain spectral components which have not been sufficiently suppressed by the low pass filter LPF. Even if complicated filter designs are used, e.g. switched capacitor filters having a very steep slope, the switching frequency may occur as spectral component in the output of the low pass filter means LPFM. Furthermore, there may be other distortion and noise components in the output of the low pass filter means LPFM which have not been sufficiently suppressed by the LPF. Such effects cause a phase-jitter in the output of the voltage-controlled oscillator VCO, i.e. a variation of the output signal frequency f
2
. Furthermore, the voltage-controlled oscillator is—even in the absence of an input control voltage—not totally stable, which causes a further intrinsic phase-jitter in the output signal frequency f
2
.
Moreover, the choice of the cut-off frequency and of the filter characteristic does not only influence the sufficient suppression of spectral components and other noise components in the output of the LPF, but also influences the tracking and locking behaviour of the entire phase-locked loop. Therefore, also regarding the maximum tracking speed and the time needed for the PLL for locking to the reference and the meantime interval error, the selection of the cut-off frequency of the LPF with respect to the frequencies f
1
/p, f
2
/q is important, in particular when f
1
/p and f
2
/q are small frequencies such that only a small number of phase comparisons can be performed.
Drawbacks of the PLL Using Two Dividers DIV
1
, DIV
2
As explained above, the relationship between the various afore mentioned parameters is of utmost importance in order to achieve
Grimm Siegfried H.
Nixon & Vanderhye P.C.
Telefonaktiebolaget LM Ericsson (publ)
LandOfFree
Phase-locked loop with improvements on phase jitter, MTIE... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Phase-locked loop with improvements on phase jitter, MTIE..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase-locked loop with improvements on phase jitter, MTIE... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2494537