Phase locked loop with improved phase-frequency detection

Oscillators – Automatic frequency stabilization using a phase or frequency... – Plural a.f.s. for a single oscillator

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331 1A, 331 8, 331 17, 331 23, 331 25, 327 43, 327553, 327558, 375376, H03L 7087, H03L 7093, H03K 526, H03H 1104

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active

056940882

ABSTRACT:
A phase locked loop including an in-phase detector (IPD), a quadrature phase detector (QPD), a frequency detector (FD), a squelch, a filter, and a voltage controlled oscillator (VCO). The in-phase detector has an IPD sample input, an IPD input, and an IPD output, where the IPD sample input is coupled to a data input. The quadrature phase detector has a QPD sample input, a QPD input, and a QPD output, where the QPD sample input is coupled to the data input. The frequency detector has a first FD input coupled to the IPD output, a second FD input coupled to the QPD output, and a FD output. The squelch has a squelch input, an enable input, and a squelch output where the squelch input is coupled to the IPD output and the squelch enable is coupled to the FD output. The filter has a filter input coupled to the squelch output and a filter output. The voltage controlled oscillator has a VCO input coupled to the filter output, a VCO in-phase output, and a VCO quadrature output. The VCO in-phase output is coupled to the IPD input and the VCO quadrature output is coupled to the QPD input. The PLL has an improved pull-in range with reduced chance of out-of-phase lock.

REFERENCES:
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patent: 5432827 (1995-07-01), Mader
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Pottbacker, Ansgar et al., "A Si Bipolar Phase and Frequency Detector IC for Clock Extraction Up to 8 Gb/s," IEEE 1992, pp. 1747-1751, IEEE Journal of Solid-State Circuits, vol. 27, No. 12, Dec. 1992.

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