Phase-locked loop with dual-mode phase/frequency detection

Details Phase-locked loop with dual-mode phase/frequency detection Phase-locked loop with dual-mode phase/frequency detection

2002-03-28

2004-07-06

Deb, Anjan K. (Department: 2858)

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

Frequency of cyclic current or voltage

C324S076740, C324S076470, C324S076820, C327S148000, C455S260000, C375S327000

Reexamination Certificate

active

06759838

ABSTRACT:

This application incorporates by reference Taiwanese application Serial No. 90110228, filed on Apr. 27, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a phase-locked loop, and more particularly to a phase-locked loop with dual-mode phase/frequency detection, which is suitable for use in wireless communication systems.
2. Description of the Related Art
A phase-locked loop (PLL) is a circuit, which generates a signal maintaining a constant phase and frequency relative to a reference signal. Phase-locked loops are widely used in wireless communications. For the years, as the wireless communications become more and more important, how to obtain a low-noise, high-speed PLL is an important topic for the industry.
Referring to
FIG. 1
, it is a block diagram illustrating a conventional PLL. In a wireless communication system, a PLL
100
is to convert an intermediate frequency (IF) signal into a radio frequency (RF) signal. The PLL
100
includes a phase/frequency detector (PFD)
102
, a loop filter (LP)
104
, a voltage-controlled oscillator (VCO)
106
, and a frequency converter
110
. The PFD
102
receives an input frequency f
IF
and a reference frequency f
ref
, and compares the input frequency f
IF
with the reference frequency f
ref
so as to obtain an output signal S
1
proportional to the phase difference between the input frequency f
IF
and the reference frequency f
ref
. After the LP
104
filters the output signal S
1
for removing undesired high-frequency components and noise from the output signal S
1
, the LP
104
outputs an output signal S
2
. The output signal S
2
is then as an input to the VCO
106
. The VCO
106
outputs an output frequency f
RF
as an output of the PLL
100
. Besides, the output frequency f
RF
is fed into the frequency converter
110
through a coupler
108
. The frequency converter
110
outputs a reference frequency f
ref
equal to a local signal frequency f
LO
minus the output frequency f
RF
.
After initialization and the operation for a settling time, the PLL
100
enters a lock state in which the reference frequency f
ref
is equal to the input frequency f
IF
and the output frequency f
RF
is given by the local signal frequency f
LO
minus the input frequency f
RF
.
When the PFD
102
of the PLL
100
is an analog PFD, the PLL
100
has a frequency response as shown in
FIG. 2
after initialized. An analog PFD detector can be implemented by an analog multiplier. Besides, an analog PFD is characterized by a lock-in range. As an input to the analog PFD, the reference frequency f
ref
has to be within the lock-in range, such as the range between the frequencies f
1
and f
2
as shown in
FIG. 2
, so that the analog PFD operates properly to cause the reference voltage varying as the phase difference between the inputs of the analog PFD. As shown in from
FIG. 2
, after the PLL
100
is initiated, the reference frequency f
ref
varies for a settling time, and then the reference frequency f
ref
enters the lock-in range while the PLL
100
is in the lock state. Since the lock-in range for an analog PFD is narrow, it takes a long settling time for the PLL
100
from the start of control of the PLL
100
to the lock state. In this way, when the analog PFD is used in a situation where frequency switching is involved, the long settling time results in a low switching speed.
A PLL that has a reduced settling time so as to increase the switching speed is described in U.S. Pat. No. 6,163,585, where a constant current source is used to achieve the reduced settling time. However, for a PLL circuit according to U.S. Pat. No. 6,163,585, the amount of the current from the constant current source must be related to the output current of a phase comparator under a condition, that is, the rate of the former and the latter must be within a specific range. Otherwise, the PLL may not lock in.
On the other hand, if a digital PFD is substituted for the PFD
102
in
FIG. 1
, the problem of having a long settling time and a low switching time can be avoided. Referring to
FIG. 3
, it shows a frequency response of the PLL
100
with a digital PFD substituted for the analog one. As the digital PFD is started with the reference frequency f
ref
at an initial frequency f
0
, it will cause the reference frequency f
ref
, in a short time, to approach the input frequency f
IF
. Since the lock-in range of a digital PFD is broad, the switching speed of the digital PFD is high. However, compared with the analog PFD, the digital PFD has the disadvantages of lower sensitivity, bad linearity, and the excessive noise in an in-band range. Therefore, the quality of the output signal of the PLL with the digital PFD is degraded.
In order to specify the differences between the conventional analog and digital FPDs,
FIGS. 4A and 4B
are two diagrams showing the relation between the phase differences and average currents of the output signals of the conventional analogy PFD and the conventional digital PFD respectively. In
FIG. 4A
, the average output current from the analog PFD, denoted by I
ave
—
A
, is fully linearly dependent on the phase difference &thgr; of the input frequency f
IF
and the reference frequency f
ref
, which corresponds to a straight line L
A
through the origin O as shown in FIG.
4
A. In
FIG. 4B
, the average output current from the digital PFD, denoted by I
ave
—
D
, is partially linearly dependent on the phase difference &thgr; of the input frequency f
IF
and the reference frequency f
ref
. That is, as shown in
FIG. 4B
, when the phase difference &thgr; is between &thgr;1 and &thgr;2, I
ave
—
D
is almost equal to zero. In this way, when the phase difference is a small value, it may occur that the digital PFD cannot discriminate between the phases of the input frequency f
IF
and the reference frequency f
ref
. Since the analog PFD provides high linearity, the PLL using the analog PFD, as being locked in, obtains the reference frequency f
ref
much more close to the input frequency f
IF
. Compared with the digital PFD, the analog PFD has lower in-band noise and better sensitivity to phase difference so that the output signal of the PLL at the output frequency f
RF
has good quality.
Hence, since the digital PFD has the deficient sensitivity to phase difference, the output signal of the PLL with the digital PFD has greater in-band noise than that of the PLL with the analog PFD. Referring to
FIG. 5
, it shows a frequency spectrum of the output frequency of a conventional PLL with the digital PFD. When the phase difference is in the range from &thgr;1 to &thgr;2, the digital PFD is unable to discriminate between its inputs so that the output signal of the PLL using the digital PFD becomes a signal centered at frequency f
RF0
with bandwidth between f
3
and f
4
, wherein f
RF0
is given by the local signal frequency f
LO
minus the input frequency f
IF
. Thus, it results in the degradation of the output signal of the PLL.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a phase-locked loop (PLL) circuit with dual-mode phase/frequency detection. By using the PLL with dual-mode phase/frequency detection, the problem that the conventional PLL using an analog phase/frequency detector provides a low switching speed is avoided. In addition, the PLL with dual-mode phase/frequency detection has the advantages of providing linear characteristics, increased switching speed, and high sensitivity.
According to the object of the invention, a phase-locked loop circuit with dual-mode phase/frequency detection is provided. The phase-locked loop circuit includes a dual-mode phase/frequency detector, a loop filter, a voltage-controlled oscillator, and a frequency converter. The dual-mode phase/frequency detector is to receive an input frequency and a reference frequency, and to obtain a detection output signal corresponding to the phase difference between the input frequency and the reference frequency. The loop filter is for filtering the detection output signal to output a filtered detection

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