Phase-locked loop with course providing damping and natural freq

Details Phase-locked loop with course providing damping and natural freq Phase-locked loop with course providing damping and natural freq

1997-07-22

1999-01-05

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

331 14, 331 17, 331 25, 331DIG2, 327156, H03L 7087, H03L 7095, H03L 7107

Patent

active

058567623

ABSTRACT:
A phase-locked loop includes a switched phase detector, a loop filter and an oscillator connected in series, as well as a device for technology compensation, in particular a course control device. An operating point is adjusted during a starting phase of the phase-locked loop through the use of the course control device in such a way that the damping and natural frequency of the phase-locked loop is independent of fluctuations in technology parameters.

REFERENCES:
patent: 3401353 (1968-09-01), Hughes
patent: 5144156 (1992-09-01), Kawasaki
patent: 5363419 (1994-11-01), Ho
patent: 5382922 (1995-01-01), Gersbach et al.
patent: 5491439 (1996-02-01), Kelkar
patent: 5703539 (1997-12-01), Gillig et al.
"A Low Jitter 5 MHz to 180 MHz Clock Synthesizer forVideo Graphics" (Shariatdoust et al.), dated May 3, 1992, pp. 24.2.1-24.2.5 IEEE 1992 Custom Integrated Circuits Conference.
"Low-Jitter and Process-Independent DLL and PLL based on Self-Biased Techniques" (Maneatis), dated Feb. 1996, vol. 39, pp. 130-131 1996 IEEE International Solid-State Circuits Conference.

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