Phase locked loop with controllable response time

Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control

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331 25, 329308, 375376, 455260, H03L 7093

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active

057480460

ABSTRACT:
An arrangement for selectively controlling the response time of a type II phase locked loop (PLL), especially one which includes a phase detector and an amplifier of a feedback type of integrator within an IC, comprises a controllable filter stage coupled in cascade with the amplifier. The controllable filter stage includes a filter section and a switching arrangement for selectively bypassing the filter section in response to a mode -determining control signal. In the described embodiment, the PLL controls the frequency of a local oscillator of a tuner and the second filter section has an amplitude versus frequency response for increasing the response time of the PLL during a fine tuning mode so that a demodulator can continue to operate properly during the fine tuning mode.

REFERENCES:
patent: 4290028 (1981-09-01), LeGrand
patent: 4670888 (1987-06-01), Smith, III
patent: 4801896 (1989-01-01), Phillips et al.
patent: 5272452 (1993-12-01), Adachi et al.
patent: 5389899 (1995-02-01), Yahagi et al.
Data Sheet "MB1507 Serial Input PLL Frequency Synthesizer" Fujitsu Limited, pp. 3-79 to 3-90, Mar. 1991.
"DSS II Product Functional Specification", Section 2.3.1 Functional Description DSS II Link Section, Thomson Consumer Electronics, Inc., Revision 4, pp. 1-4, Sep. 22, 1995.
Preliminary Specification, "2.5 GHz bi-directional 12C-BUS Controlled Synthezizer TSA5055T", Phillips Semiconductors, pp. 3489, 3492-3497, Nov. 1991.
Data Sheet, "2.0 GHz PLL Frequency Synthesizers Include On-Board 64/65 Prescalers, MC145200, MC145201", Motorola Inc., pp. 1-20, 1993.

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