Phase-locked loop with conditioned charge pump output

Details Phase-locked loop with conditioned charge pump output Phase-locked loop with conditioned charge pump output

2002-01-28

2004-03-23

Shingleton, Michael B (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S016000, C331S018000, C331S055000, C331S185000

Reexamination Certificate

active

06710665

ABSTRACT:

TECHNICAL FIELD
The present invention relates to phase-locked loop systems, and more particularly to phase-locked loop systems where charge pump output is conditioned in the proportional control path of the loop to improve jitter performance, and/or where the charge pump currents are scaled to vary performance of the phase-locked loop.
BACKGROUND OF THE INVENTION
Phase-locked loop (PLL) systems are used extensively in analog and digital circuits. These systems typically include a phase frequency detector (PFD), charge pump and voltage controlled oscillator (VCO) connected in a feedback configuration. The VCO produces the output signal of the PLL, and the various components of the PLL cooperate to cause the output signal to tend toward and eventually lock on to a desired output frequency, which is based on a reference signal applied as an input to the PFD. For example, many PLL systems are configured to produce an output signal having the same frequency as the input signal, or having an output frequency which is a factor x/y of the input frequency.
The output signal tracks the desired output frequency through operation of a feedback mechanism, in which the output of the VCO is fed back to the PFD as a feedback signal via a feedback path. The phase frequency detector receives the reference signal and the feedback signal, and produces an error signal based on discrepancies between the actual phase and frequency of the output signal and the desired phase and frequency. The error signals from the PFD are applied to the charge pump, which in turn produces signals that control the oscillation frequency of the VCO.
Minimizing or reducing uncontrolled jitter in the output signal is an important design issue in PLL systems. Jitter is variation in the phase and/or frequency of the output signal when the system is aligned or very nearly aligned. Most PLL systems exhibit some amount of jitter in the output signal. Indeed, many PLL systems have what is known as a “dead band,” or a range of output alignments through which the system exerts little or no control over the output signal. This problem is addressed in some designs through phase frequency detectors configured to generate simultaneous canceling error signals when the system is in lock. Despite this solution, many of these systems still exhibit an unacceptably high level of jitter, particularly where the systems are used to multiply the frequency of the reference signal. Also, even where jitter is reduced to an acceptable level, many such systems exhibit an undesirable amount of static phase offset in the output signal, that is, an average phase discrepancy between the output signal and the desired phase.
In addition to the above problems, many existing PLL systems have other shortcomings which can have undesirable affects on the PLL output signal. For example, some systems suffer from undesired signal coupling between the various PLL components, which can lead to noise or jitter in the output signal. In other designs, the VCO and other PLL components are susceptible to voltage variations or noise coupled into the system from the voltage supply or other sources.
In addition, conventional phase-locked loops typically include components designed to operate under fixed or relatively fixed conditions. This can reduce the flexibility of the design, and constrain its use to a limited range of applications. For example, many PLL systems are designed for frequency multiplication by a predetermined scale factor, or are designed with predetermined dynamic characteristics (e.g., damping and bandwidth response) that are fixed at design time.
SUMMARY OF THE INVENTION
The present invention provides a phase-locked loop system configured to cause an output signal to tend toward a desired output frequency. The phase-locked loop system includes a charge pump system configured to produce a charge pump output based on differences detected between the output signal and the desired output frequency. The phase-locked loop further includes an oscillator operatively coupled with the charge pump system and configured to produce the output signal based on the charge pump output. The charge pump system is configured to selectively effect proportional control over the output signal by producing a correcting pulse having a duration and applying the correcting pulse to a proportional control path of the phase-locked loop system. The charge pump system also includes a correcting circuit configured to store a correcting charge corresponding to the correcting pulse, and then output the correcting charge over a period of time that is greater than the duration of the correcting pulse.
According to another aspect of the invention, a method is provided for reducing jitter in a phase-locked loop system. The method includes receiving a correcting pulse, storing a charge based on the correcting pulse, and outputting the stored charge over a period of time that is greater than the duration of the correcting pulse.
According to further aspects of the invention, phase-locked loops are provided that employ programmable current mirrors, and other structures and methods, to reduce charge pump current within the phase-locked loop.


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Delmot et al. “A Fully-Configurable GSM BTS Controller and GMSK-EDGE Baseband Transmitter IC” IEEE Solid-State Conference Feb. 5-7, 2001 pp. 352-353.

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