Phase-locked loop with capacitive voltage divider for reducing j

Details Phase-locked loop with capacitive voltage divider for reducing j Phase-locked loop with capacitive voltage divider for reducing j

1997-08-20

1999-03-30

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

331 8, 331 34, 331 74, 331108C, 331 57, 331177R, 327156, H03L 708, H03L 7099

Patent

active

058894390

ABSTRACT:
In a phase-locked loop comprising a phase detector (1), a loop filter (5) and a controlled oscillator (17) which are arranged on a common integrated circuit, interferences coupled into the substrate of the integrated circuit by other parts of the circuit are suppressed. In a first embodiment of the invention, this object is achieved in that the controlled oscillator (17) is preceded by a capacitive voltage divider (9) which comprises at least two capacitances (10, 12), the controlled oscillator (17) is controlled in dependence upon the output signal of the capacitive voltage divider (9), and the capacitive voltage divider (9), together with the phase detector (1), the loop filter (5) and the controlled oscillator (17) is arranged on an integrated circuit. In accordance with a second embodiment of the invention, the reduction of interference is achieved in that the controlled oscillator (17) has a differential structure and comprises at least two voltage-controlled current sources (18, 19) whose circuits are coupled to a power supply potential and to a substrate on which the integrated circuit is arranged, the controlled oscillator (17) has an output stage (20) which is arranged behind the voltage-controlled current sources (18, 19) and generates two differential digital signals in dependence upon the differential signals applied thereto, which differential digital signals are generated with a high edge steepness by means of switching between two potentials and are applied to amplifier stages (56, 57) which are arranged between power supply potential and reference potential and supply two differential output signals operating at reference potential.

REFERENCES:
patent: 5036295 (1991-07-01), Kamitani
patent: 5221911 (1993-06-01), Kasperkovitz et al.
patent: 5402425 (1995-03-01), Bladh
patent: 5442325 (1995-08-01), Bosshart
patent: 5467060 (1995-11-01), Miyashita
patent: 5483205 (1996-01-01), Kawamura
patent: 5523724 (1996-06-01), Assar et al.
Philips Integrated Circuits Data Sheet SAA7110; SAA7110A. One Chip Front-end 1 (OCF1) Oct. 18, 1995.
Philips Integrated Circuits Data Sheet SAA7111; Video Input Processor (VIP) Oct. 30, 1996.
Philips Integrated Circuits Data Sheet SAA7196; Digital Video Decoder, Scaler and Clock Generator Circuit (DESCPro) Nov. 4, 1996.

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