Phase-locked loop with built-in self-test of phase margin...

Details Phase-locked loop with built-in self-test of phase margin... Phase-locked loop with built-in self-test of phase margin...

2000-04-13

2001-07-17

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

C331S017000, C331S023000, C331S044000, C327S156000, C327S158000, C324S600000, C324S602000, C324S605000, C324S606000

Reexamination Certificate

active

06262634

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to semiconductor integrated circuits and, more particularly, to a circuit for measuring the phase margin and loop gain of a phase-locked loop.
A typical PLL includes a phase/frequency detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO) and a frequency divider. The VCO generates a clock signal with a phase and frequency that is a function of the voltage applied to the oscillator. The phase/frequency detector detects a phase difference between the VCO output and the input signal. The phase/frequency detector generates a phase control signal as a function of the difference and applies the phase control signal to the charge pump, which increases or decreases the voltage across the loop filter. This voltage is applied to the VCO for controlling the oscillation frequency and phase. Once a PLL has locked a feedback signal onto the phase and frequency of a reference input signal, any remaining phase error between the reference feedback signal and the input signal is known as “jitter”.
The performance of a second order PLL can be defined in terms of a damping factor (&zgr;) and an un-damped natural frequency (&ohgr;
n
). These performance characteristics determine the phase margin (&phgr;
m
) and the loop gain (K) for the PLL. In integrated circuit applications, it is important that these performance characteristics lie within predefined specifications. However, the phase margin and loop gain can vary by as much as a factor of two or more from one integrated circuit to the next due to variations in process, supply voltage and temperature, which are known as “PVT”. Variations in the phase margin and loop gain that exceed specified margins can lead to difficulties in clock synchronization, accurate recovery of serial data streams and other functions commonly performed by PLLs.
SUMMARY OF THE INVENTION
One aspect of the present invention is directed to a phase-locked loop (PLL), which includes a PLL reference input, a PLL output and a phase detection loop coupled between the PLL reference input and the PLL output. The phase detection loop has a loop filter node. A delay element is coupled within the phase detection loop and has a variable delay, which can be increased to a critical delay at which the phase detection loop becomes unstable. A demodulator is coupled to the loop filter node and is adapted to demodulate a modulated voltage on the loop filter node. The demodulator has a demodulated output with a characteristic representative of a phase margin of the phase detection loop when the delay element has at least the critical delay.
Another aspect of the present invention is directed to a method of measuring phase margin of a phase-locked loop (PLL) having a reference input. The method includes: (a) applying a reference clock to the reference input; (b) providing a variable delay within the PLL; (c) increasing the variable delay until the PLL becomes unstable; and (d) generating a phase margin output related to the phase margin as a function of the variable delay at which the PLL becomes unstable.
Yet another aspect of the present invention is directed to a phase-locked loop (PLL), which includes a PLL reference input, a PLL output and a phase detection loop coupled between the PLL reference input and the PLL output. A delay circuit is coupled to the phase detection loop for introducing a delay into the phase detection loop and for varying the delay until the phase detection loop becomes unstable. A phase margin measuring circuit measures a phase margin of the PLL as a function of the delay introduced by the delay means when the phase detection loop becomes unstable.


REFERENCES:
patent: 4754216 (1988-06-01), Wong
F. M. Gardner, “Charge-Pump Phase-Lock Loops”, IEEE Transactions on Communications, vol. COM-28, No. 11, Nov. 1980, pp. 1849-58.
W. F. Egan, “Phase Lock Basics”, Wiley Interscience Publications, New York, 1998, pp. 90-91.
P. V. Brennan, “Phase Locked Loops: Principles and Practice”, McGraw-Hill, New York, 1996, p. 35.
D. H. Wolaver, “Phase-Locked Loop Circuit Design”, PTR Prentice Hall, New Jersey, 1991, pp. ix-x.

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