Phase locked loop with bandwidth ramp

Details Phase locked loop with bandwidth ramp Phase locked loop with bandwidth ramp

1989-12-18

1990-09-04

Pascal, Robert J.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

331 25, H03L 700

Patent

active

049547887

ABSTRACT:
A phase locked loop that operates on an input signal received from a disk drive and similar data processing system peripherals, where the input signal has a preamble portion and a data portion. The phase locked loop providing a digital clock signal which is phase locked to the preamble portion. This is accomplished by adjusting the loop response time so that it monotonically decreases in amplitude beginning at a time when the phase locked loop receives the preamble portion and continuing to monotonically decrease during at least a portion of the time that the phase locked loop receives the data portion. The response time may be monotonically decreased in any suitable fashion, such as linearly or exponentially. A specific embodiment of a linearly decreasing signal generator used with a charge pump is disclosed. The results of computer simulations showing a decrease in lock acquisition time and increased noise immunity with shortened preamble time are also discussed.

REFERENCES:
patent: 4704586 (1987-11-01), Wahl et al.
patent: 4712076 (1987-12-01), Cronch et al.
Digital Equipment Corp. RL01/RL02 Disk Controller, circa 1979.

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