Phase-locked loop with a digital calibration loop and an...

Details Phase-locked loop with a digital calibration loop and an... Phase-locked loop with a digital calibration loop and an...

2006-03-28

2008-09-02

Pascal, Robert J. (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331S010000, C331S014000, C331S044000

Reexamination Certificate

active

07420427

ABSTRACT:
A phase-locked loop (PLL) architecture (100) is provided that includes a voltage-controlled oscillator (VCO) (116). The PLL architecture (100) also includes a digital calibration loop (132) coupled to the VCO (116). The digital calibration loop (132) implements a digital filter (126) to provide a digital control to the VCO (116) for centering a VCO frequency output. The PLL architecture (100) also includes an analog calibration loop (130) coupled to the VCO (116). The analog calibration loop (130) provides an analog control to the VCO (116) for adjusting the centered VCO frequency output.

REFERENCES:
patent: 5955928 (1999-09-01), Smith et al.
patent: 6356158 (2002-03-01), Lesea
patent: 6545547 (2003-04-01), Fridi et al.
patent: 6903615 (2005-06-01), Landman et al.
patent: 6952124 (2005-10-01), Pham
patent: 7042253 (2006-05-01), Su et al.
patent: 7103337 (2006-09-01), Uozumi et al.
patent: 7221921 (2007-05-01), Maligeorgos et al.

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