Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control
Reexamination Certificate
1997-09-03
2001-04-10
Kinkead, Arnold (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Particular error voltage control
C331SDIG002, C331S00100A, C327S536000, C327S157000
Reexamination Certificate
active
06215361
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a phase-locked loop including a device for limiting the charge pump current. It applies, for example, to the field of processing of synchronization signals relative to display on screens.
2. Discussion of the Related Art
To control the display of data and images on a monitor or a television screen and, more specifically, to control the scanning of an electron beam on a screen, synchronization signals are used. These synchronization signals add to the effective signal, that is, to the signal representative of the data or images to be displayed. They contain time information that enables spotting the beginning of lines (horizontal synchronization) and the beginning of frames (vertical synchronization). According to these signals, deflectors which direct the electron beam scanning the screen are controlled.
In practice, the synchronization signals are logic pulse signals mainly defined by the polarity, positive or negative, of their pulses, their pulse recurrence frequency and duration.
Taking into account of the signals is generally performed on the one hand by means of automatic gain control loops, for vertical synchronization, and on the other hand, by means of phase-locked loops, for horizontal synchronization.
FIG. 1
illustrates a phase-locked loop
2
of known type, implementing a phase/frequency type comparator. Such a loop is for example implemented in circuits TDA 9103 and TDA 9105 produced by SGS-THOMSON Microelectronics, to process horizontal synchronization signals. It includes a comparator
4
of phase/frequency type, a charge pump
6
, a capacitive filter
8
, a voltage-controlled oscillator
10
(VCO), and a phase adjustment device
12
.
Comparator
4
is used to compare an input pulse signal SIN received on an input
14
, with a reference pulse signal SREF supplied by phase adjustment device
12
.
Depending on the comparison, comparator
4
controls charge pump
6
. This pump will charge or discharge filter
8
, so that the voltage VREF produced by the filter will be representative of the result of the comparison between SIN and SREF.
Oscillator
10
generates, based on voltage VREF, a triangular output signal SOUT, the frequency of which is proportional to voltage VREF. Signal SOUT is provided, on the one hand, on an output
16
and, on the other hand, to device
12
.
Device
12
generates a reference signal SREF based on signal SOUT and on a phase adjustment control signal ADJ. Signal ADJ is received on an input
18
and is used to position the fronts in signal SREF, the frequency of the pulses in signal SREF being identical to the recurrence frequency of signal SOUT.
Once signals SIN and SREF are in phase and at the same frequency, voltage VREF settles. Loop
2
has been “locked”.
Finally, it should be noted that signal SIN is supplied by an input interface
20
which enables, typically, from a received synchronization signal HSYNC, generation of a signal SIN of fixed polarity. Signal HSYNC can be a horizontal synchronization signal with any polarity, or even a composite type signal, in which case signal SIN is obtained by extracting the horizontal synchronization pulses.
FIG. 2
illustrates an example of comparator
4
, of phase/frequency type. The comparator could be a simple phase comparator. The use of a comparator of phase/frequency type enables avoiding a locking of the loop on a frequency which is a multiple of the frequency of input signal SIN. A problem is that this type of comparator is very sensitive to the absence of pulses and to the presence of additional pulses (such as equalizing pulses).
The comparator includes an input
22
for receiving signal SIN, an input
24
for receiving signal SREF, an output
26
for supplying a charge control signal HIGH and an output
28
for supplying a discharge control signal LOW. A two-input NOR-type logic gate
30
receives signals SIN and HIGH on its inputs. It provides a logic signal G
1
. A two-input NOR-type logic gate
32
receives on its inputs signal SREF and a logic signal G
6
, which is the inverse of signal LOW. It generates a logic signal G
2
.
An RS-type flip-flop
34
receives signal G
1
on its set input S. It receives a RESET signal on its reset input R. It provides a logic signal G
3
on its output Q. An RS-type flip-flop
36
receives signal G
2
on its set input. Its receives signal RESET on its reset input. It provides a logic signal G
4
.
A four-input NOR-type logic gate
38
receives signals G
1
, G
2
, G
3
, and G
4
on its inputs and provides a logic signal G
5
. Signal G
5
is supplied to a delay circuit
39
. Circuit
39
generates signal RESET, this signal being identical to signal G
5
, with a delay.
A three-input NOR-type gate
40
receives signals G
1
, G
3
and RESET on its inputs and provides signal HIGH. Finally, a three-input NOR-type logic gate
42
receives signals G
2
, G
4
, and RESET on its inputs and provides signal G
6
. Signal G
6
is supplied to an inverter
43
which provides signal LOW.
FIG. 3
illustrates an example of charge pump
6
.
It includes an input
44
for receiving control signal HIGH, an input
46
for receiving control signal LOW, an output
48
connected to filter
8
, a supply input
50
for receiving a positive supply potential VCC and a supply input
52
for receiving a ground potential GND.
Pump
6
includes two current mirrors
54
and
56
.
A first mirror
54
is formed by two transistors
58
and
60
, for example of PNP type. Their emitters are connected to input
50
. Their bases are interconnected and connected to the collector of transistor
58
. A switch
62
, controlled by signal HIGH, enables connection of these bases to input
50
.
A second mirror
56
is formed by two transistors
64
and
66
, for example of NPN type. Their emitters are connected to input
52
. Their bases are interconnected and connected to the collector of transistor
64
. A switch
68
, controlled by signal LOW, enables connection of these bases to input
52
.
The collectors of transistors
58
and
64
arc interconnected by means of a resistor
70
. The collectors of transistors
60
and
66
are connected to output
48
.
The current i running through transistors
58
or
64
is equal to (VCC−Vbe)/R
1
, R
1
being the value of resistor
70
and Vbe the base/emitter voltage of these transistors. When switch
62
is open, this current is copied in transistor
60
. Filter
8
is then charged with a charge current Ich=i. When switch
68
is open, current i is copied in transistor
66
. The filter is then discharged with a discharge current Idch=i.
FIG. 4
illustrates an example of filter
8
. It is a C-R-C-type capacitive filter which includes a first input
72
, connected to output
48
of the charge pump and to an input of oscillator
10
, and a second input
74
receiving the ground potential. Voltage VREF provided by the filter is the potential difference between inputs
72
and
74
.
The filter includes a first capacitor
76
, mounted between inputs
72
and
74
. It also includes a resistor
78
and a second capacitor
80
mounted in series between these same inputs. Capacitor
80
, of high value (for example, 4.7 microfarads or more) is used to maintain voltage VREF. It avoids having a fall (to potential GND) and a rise (to potential VCC) of voltage VREF that is too rapid when the edges in signals SIN and SREF are distant. Capacitor
76
, of low value (for example, around 10 nanofarads), enables a quick adaptation of voltage VREF to the result of the comparison between signals SIN and SREF, when the edges in these signals are close.
In practice, the filter is implemented in discrete components, the other elements being currently implemented most of the time in the form of an integrated circuit.
Referring to
FIGS. 5
a
to
5
d
, the operation of a portion of the loop will now be briefly described, and more specifically, the production of voltage VREF (illustrated in
FIG. 5
d
) as a function of signals SIN and SREF (illustrated in
FIG. 5
a
and
5
b
).
FIG
Berger Philippe
Cirot Eric
Lebouleux Nicolas
Galanthay Theodore E.
Kinkead Arnold
Morris James H.
SGS-Thomson Microelectronics S.A.
Wolf Greenfield & Sacks P.C.
LandOfFree
Phase-locked loop with a charge pump current limiting device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Phase-locked loop with a charge pump current limiting device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase-locked loop with a charge pump current limiting device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2437301