Phase locked loop, voltage controlled oscillator, and...

Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular frequency control means

Reexamination Certificate

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C331S1070SL, C331S167000

Reexamination Certificate

active

07830212

ABSTRACT:
A phase locked loop, voltage controlled oscillator, and phase-frequency detector are provided. The phase locked loop comprises a phase-frequency detector (PFD), a loop filter (LF), a voltage controlled oscillator (VCO), and a 3-stage frequency divider. The PFD receives a reference signal and a feedback signal to determine phase and frequency errors. The LF), coupled to the phase-frequency detector, filters the phase and frequency errors to generate a control voltage. The VCO, coupled to the loop filter, generates a VCO output signal according to the control voltage. The 3-stage frequency divider, coupled to the voltage controlled oscillator, divides the frequency of the VCO output signal 3 times to generate the feedback signal.

REFERENCES:
patent: 2007/0026816 (2007-02-01), Heidari et al.
patent: 2008/0164955 (2008-07-01), Pfeiffer et al.
patent: 1992528 (2007-07-01), None
IEEE Journal of Solid-State Circuits, vol. 41, No. 1, Jan. 2006, “A 60-GHz CMOS Receiver Front-End”, Behzad Razavi, Fellow, IEEE.
ISSCC 2004 / Session 24 / TD: Wireless Trends: Low-Power and 60GHZ / 24.4, “Design of CMOS for 60GHz Applications” Chinh H. Doan et al.
IEEE Journal of Solid-State Circuits, vol. 41, No. 5, May 2006, “High-Speed Circuit Designs for Transmitters in Broadband Data Links” Jri Lee, Member IEEE.
ISSCC 2006/Session 32/ PLLs, VCOs, and Dividers/ 32.8, “70GHz CMOS Harmonic Injection-Locked Divider” Ken Yamamoto et al.
ISSCC 2006/Session 32/PLLs, VCOs, and Dividers/ 32.7, “A Combined Dynamic and Static Frequency Divider for a 40GHz PLL in 80nm CMOS,” George Von Buren et al.
IEEE Journal of Solid-State Circuits, vol. 39, No. 4, Apr. 2004, “A 40-GHz Frequency Divider in 0.18-μm CMOS Technology” Jri Lee et al.
IEEE Journal of Solid-State Circuits, vol. 38, No. 12, December,“A 40-Gb/s Clock and Data Recovery Circuit in 0.18-μm CMOS Technology,” Jri Lee et al.
IEEE Journal of Solid-State Circuits, vol. 38, No. 11, Nov. 2003, “A Low-Power Adaptive Bandwidth PLL and Clock Buffer With Supply-Noise Compensation” Mozhgan Mansuri et al.
ISSCC 2001/ Session 26/ Wireless Building Blocks II/ 26.3, “A 19GHz 0.5mW 0.35μm CMOS Frequency Divider with Shunt-Peaking Locking-Range Enhancement” Hui Wu et al.
IEEE Journal of Solid State Circuits, vol. 36, No. 11, Nov. 2001, “A Low-Jitter 125-1250-MHz Process-Independent and Ripple-Poleless 0.18μm CMOS PLL Based on a Sample-Reset Loop Filter” Adrian Maxim et al.
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IEEE Journal of Solid-State Circuits, vol. 41, No. 4, Apr. 2006, A 20-GHz Phase-Locked Loop for 40-GB/s Serializing Transmitter in 0.13-μm CMOS Jaeha Kim et al.
IEEE Journal of Solid-State Circuits, vol. 39, No. 11, Nov. 2004, “A 2.5-10-GHz Clock Multiplier Unit With 0.22-ps RMS Jitter in Standard 0.18-μm CMOS” Remco C. H. Van De Beek et al.
ISSCC 2006/ Session 32/ PLLs, VCOs, and Dividers/32.5, “A 6.25GHz 1V LC-PLL in 0.13μm CMOS” Richard Gu et al.
ISSCC 2005/Session 8/ Circuits for High-Speed Links and Clock-Generators/8.5, “A 1V 24GHz 17.5mW PLL in 0.18μm CMOS” Alan W.L. Ng et al.
IEEE/1991, “Fast Acquisition Frequency Synthesizer with the Multiple Phase Detectors” Duk-Kyu Park et al.
ISSCC 2006/ Session 32/ PLLs, VCOs, and Dividers/ 32.4,“A Spur Suppression Technique for Phase-Locked Frequency Synthesizers” Tai-Cheng Lee et al.
ISSCC 2005/Session 21/ TD: RF Trends: Above-IC Integration and MM-Wave/21.9, “Fully Integrated BiCMOS PLL for 60 GHz Wireless Applications” Wolfgang Winkler et al.
IEEE Journal of Solid-State Circuits, vol. 41, No. 5, May 2006,“A Fully V-Band PLL MMIC Using 0.15-μm GaAs pHEMT Technology” Jinho Jeong et al.
English language translation of abstract of CN 1992528 (published Jul. 4, 2007).

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