Phase locked loop using sample and hold after phase detector

Details Phase locked loop using sample and hold after phase detector Phase locked loop using sample and hold after phase detector

2001-10-24

2003-05-27

Mis, David C. (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

C331S008000, C331S014000, C331S016000, C327S156000

Reexamination Certificate

active

06570457

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to phase locked frequency synthesizers, and in particular to phase locked loops that suppress the leakage of spurious energy from the phase detector to the controlled oscillator.
2. Discussion of the Related Art
A phase locked loop (PLL) is a negative feedback system that maintains a constant phase and zero frequency difference between a variable frequency and a reference frequency. Conventional PLL's include a phase detector element to compare the frequency and phase of an oscillator to that of the reference frequency. The oscillator is then controlled to maintain the constant phase and frequency difference.
Often, it is desirable to design a PLL so that the PLL can be rapidly tuned from one lock point (or frequency) to another. This is accomplished through a “wide” PLL control system bandwidth. However, the “sampling” nature of the phase detector limits the PLL control system bandwidth and therefore tuning speed to substantially less than the sampling rate. Further, imperfections in the phase detector produce undesirable leakage of the phase detector sampling (reference) frequency into the forward path of the PLL control system. Filtering is generally employed to attenuate the impact of the leakage. The additional filtering causes an even greater reduction of PLL bandwidth below the sampling rate.
Still another problem occurs in PLLs having multiple bandwidths. In multi-bandwidth PLLs, a wide bandwidth is employed for PLL acquisition and a narrower bandwidth is switched to for tracking. The wide acquisition bandwidth improves acquisition speed, while the narrow tracking bandwidth provides increased tracking. accuracy. In such a design if additional filtering is used to attenuate leakage, it is necessary to use a switch(es) to alter the filtering time constant to accommodate the separate bandwidths. Physically realizable switches and the associated circuits suffer from a phenomenon, known as “charge injection”, which introduces a disturbance into the other circuit elements at the time the switch is activated. Charge injection is also commonly referred to as “switch feedthrough” and generally occurs as the result of the switch control signal entering the signal path via parasitic capacitive coupling. The resulting effect is the injection of an amount of charge equal to the voltage change in the control signal times the size of the parasitic capacitor. The disturbance caused by charge injection may form a new limitation on the speed of the phase locked loop tuning because the disturbance must be resolved by the slower tracking bandwidth PLL control system.
SUMMARY OF THE INVENTION
The phase locked loop system and method provides a system and method for generating a variable output frequency signal. The phase locked loop includes a controlled oscillator to generate the variable output frequency signal in response to a tune signal. A feedback frequency divider coupled to the controlled oscillator is operable to generate a divided frequency signal from the variable output frequency signal. A phase detector that is driven by a reference frequency generates an error signal representing a difference between the reference frequency signal and the divided frequency signal. A sample and hold circuit is activable in response to a gating signal related to the reference frequency, to sample the error signal and generate a sampled signal. A loop filter filters the sampled signal and generates the tune signal.
For a more complete understanding of the invention, its objects and advantages, reference may be had to the following specification and to the accompanying drawings.


REFERENCES:
patent: 5920233 (1999-07-01), Denny
patent: 6223061 (2001-04-01), Dacus et al.

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