Phase-locked loop using a random-access memory

Details Phase-locked loop using a random-access memory Phase-locked loop using a random-access memory

1999-07-06

2001-01-23

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S150000, C327S106000, C331S034000

Reexamination Certificate

active

06177820

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a phase-locked loop (PLL), and more specifically to a PLL using a random access memory.
2. Description of the Related Art
It is known in the art that a PLL is essentially a closed loop electric servomechanism whose output is locked onto, and will track a reference signal.
Before turning to the present invention, it is deemed advantageous to briefly describe, with reference to
FIG. 1
, a conventional PLL.
A PLL
10
, shown in
FIG. 1
, is comprised of a phase detector
12
, a control voltage generator
14
, a voltage-controlled oscillator (VCO)
16
, and a frequency divider (or frequency demultiplier)
18
. A reference clock CLK
0
is fed to the phase detector
12
which also receives a clock CLK
2
from the frequency divider
18
. The phase detector
12
compares the phases of the two clocks CLK
0
and CLK
2
, and generates an error signal which is proportional to the phase difference between the two clocks. Although not shown in
FIG. 1
, the error signal is typically filtered by a loop filter (low-pass filter) and is applied to the control voltage generator
14
whose output is adjusted to generate a clock CLK
1
from the VCO
16
with a predetermined clock rate (frequency). The clock CLK
1
is applied to an external circuit (not shown) and to the frequency divider
18
. Assuming that a divide value of the frequency divider
18
is Nv, then the frequency of the clock CLK
1
is expressed by Nv multiplied by the frequency of the reference clock CLK
0
.
The above-mentioned conventional PLL has failed to pay any attention to the quality of the reference clock CLK
0
. In other words, the PLL of
FIG. 1
is unable to determine the quality of the reference clock CLK
0
. Therefore, the PLL of
FIG. 1
has suffered from the following difficulties. That is, the output clock CLK
1
is undesirably deteriorated in the case where the clock rate of the reference clock CLK
0
becomes unstable, and in the case where the wave-form of the reference clock CLK
0
is disturbed due to noises superimposed thereon, and in the case where the reference clock CLK
0
is instantaneously terminated.
SUMMARY OF THE INVENTION
It is therefore an object of the present to provide a PLL which utilizes a random-access memory (RAM).
Another object of the present invention is to provide a PLL which makes use of a random-access memory and is able to generate a clock signal which is stable against undesirably disturbed reference clock.
In brief, these objects are achieved by a phase-locked loop (PLL) utilizing a RAM is disclosed. The RAM is provided to store a reference clock and a clock to be controlled. The PLL further comprises a voltage-controlled oscillator section controls a phase of the clock to be controlled. The PLL further comprises a controller for retrieving, from the RAM, data of said reference clock and said clock to be controlled. The controller determines a phase difference between said reference clock and said clock to be controlled. Additionally, the controller generating a control signal so as to reduce said phase difference and applying said control signal to said voltage-controlled oscillator section.


REFERENCES:
patent: 5673004 (1997-09-01), Park
patent: 5894246 (1999-04-01), Barnett et al.

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