Phase locked loop tuning system including stabilized time interv

Details Phase locked loop tuning system including stabilized time interv Phase locked loop tuning system including stabilized time interv

1978-07-17

1980-01-08

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

325419, 325453, 325468, 331 25, H03B 304

Patent

active

041829948

ABSTRACT:
A phase locked loop (PLL) tuning system for generating a local oscillator signal includes a programmable divider having a programmable division factor related to the frequency of the local oscillator signal. The programmable factor is determined by the duration of output pulses generated by a triggerable circuit in response to input trigger pulses generated by the PLL. The duration of the output pulses is adjustable by means of a potentiometer included in an R-C time constant network associated with the triggerable circuit. A reference divider associated with the PLL generates reference trigger pulses and reference time pulses in a substantially fixed time relationship during time intervals between output pulses generated in response to the input trigger pulses. The triggerable circuit generates comparison output pulses in response to the reference trigger pulses. The fixed time interval is related to the nominal values of the durations of the comparison output pulses. A comparison circuit generates a control signal in accordance with the time relationship between the termination of the comparison output pulses and the reference time pulses. The control signal is coupled to the time constant network to reduce deviations between the duration of the comparison output pulses and the fixed time relationship.

REFERENCES:
patent: 4097810 (1978-06-01), Aschwanden
Schmid et al., Electronic Design, No. 26, Dec. 19, 1968, pp. 61-65.
Schmid et al., Electronic Design, No. 1, Jan. 4, 1969, pp. 104-108.

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