Phase-locked loop system and method using an auto-ranging,...

Details Phase-locked loop system and method using an auto-ranging,... Phase-locked loop system and method using an auto-ranging,...

2000-11-08

2002-10-22

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

C331S004000, C331S034000, C331S00100A, C331SDIG002, C331S00100A

Reexamination Certificate

active

06469584

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to phase-locked loops and, more particularly, to a system and method for acquiring and tracking a data signal with a voltage controlled oscillator (VCO) having selectable frequency ranges and a selectable frequency sweep window.
2. Description of the Related Art
Phase-locked loops (PLLs) and clock recovery circuits (CRCs) find wide application in areas such as communications, wireless systems, digital circuits, and disk drive electronics (parts of the following background are excerpts from Behzad Ravavi, “Design of Monolithic Phase-Locked Loops and Clock Recovery Circuits—A Tutorial”). While the concept of phase locking has been in use for more than half a century, monolithic implementation of PLLs and CRCs has become possible only in the last twenty years, and popular in the last ten years. Two factors account for this trend: the demand for higher performance and lower cost in electronic systems, and the advance of integrated-circuit (IC) technologies in terms of speed and complexity.
In many systems, data is transmitted or retrieved without any additional timing reference. In optical communications, for example, a stream of data flows over a single fiber with no accompanying clock, but the receiver must eventually process the data synchronously. Thus, the timing information (e.g., the clock) must be recovered from the data at the receive end. Most clock recovery circuits employ phase locking.
An ideal voltage-controlled oscillator (VCO) generates a periodic output whose frequency is a linear function of a control voltage &ngr;
cont
:
&ohgr;
out
=w
FR
+K
VCO
V
cont
where &ohgr;
FR
is the “free-running” frequency and K
VCO
is the “gain” of the VCO (specified in rad/s/V). Since phase is the time integral of frequency, the output of a sinusoidal VCO can be expressed as:
y
(
t
)=
A
cos(&ohgr;
FR
t+K
VCO
∫
−00
t
V
cont
dt
).
In practical VCOs, K
VCO
exhibits some dependence on the control voltage and eventually drops to zero as |V
cont
| increases.
A VCO is considered to be a linear time-invariant system, with the control voltage as the system's input and the excess phase of the output signal as the system's output. Since the excess phase is:
&phgr;
out
(
t
)=
K
VCO
∫V
cont
dt,
the input/output transfer function is:
Φ
out
⁡
(
s
)
V
cont
⁡
(
s
)
=
K
VCO
s
.
The above equation reveals an interesting property of VCOs: to change the output phase, we must first change the frequency and let the integration take place. For example, suppose for t<t
0
, a VCO oscillates at the same frequency as a reference, but with a finite phase error. To reduce the error, the control voltage, V
cont
, is stepped by +&Dgr;V at t=t
0
, thereby increasing the VCO frequency and allowing the output to accumulate phase faster than the reference. At t=t
1
, when the phase error has decreased to zero, V
cont
returns to its initial value. Now, the two signals have equal frequencies and zero phase difference. Note also that the same goal can be accomplished by lowering the VCO frequency during this interval.
An ideal phase detector (PD) produces an output signal whose dc value is linearly proportional to the difference between the phases of two periodic inputs:
{overscore (V
out
)}
=K
PD
&Dgr;&phgr;
where K
PD
is the “gain” of the phase detector (specified in V/rad), and &Dgr;&phgr; is the input phase difference. In practice, the characteristic may not be linear or even monotonic for large &Dgr;&phgr;. Furthermore, K
PD
may depend on the amplitude or duty cycle of the inputs.
A phase-locked loop is a feedback system that operates on the excess phase of nominally periodic signals. This is in contrast to familiar feedback circuits where voltage and current amplitudes, and their rate of change are of interest. A simple PLL, consists of a phase detector, a low-pass filter (LPF), and a VCO. The PD serves as an “error amplifier” in the feedback loop, thereby minimizing the phase difference, &Dgr;&phgr;, between x(t) and y(t). The loop is considered “locked” if &Dgr;&phgr; is constant with time, a result of which is that the input and output frequencies are equal.
In the locked condition, all the signals in the loop have reached a steady state and the PLL operates as follows. The phase detector produces an output whose dc value is proportional to &Dgr;&phgr;. The low-pass filter suppresses high-frequency components in the PD output, allowing the value to control the VCO frequency. The VCO then oscillates at a frequency equal to the input frequency and with a phase difference equal to &Dgr;&phgr;. Thus, the LPF generates the proper control voltage for the VCO.
It is important to note that in the above example the loop locks only after two conditions are satisfied: 1) &ohgr;
out
has become equal to &ohgr;
in
; and, 2) the difference between &phgr;
in
, and &phgr;
out
has settled to its proper value. If the two frequencies become equal at a point in time but &Dgr;&phgr; does not establish the required control voltage for the VCO, the loop must continue the transient, temporarily making the frequencies unequal again. In other words, both “frequency acquisition” and “phase acquisition”, or “tracking”, must be completed. This is, of course, to be expected because for lock to occur again, all the initial conditions of the system, including the VCO output phase, must be updated.
Acquisition range is a critical parameter because 1) it trades directly with the loop bandwidth, and therefore, VCO gain. For example, if an application requires a small loop bandwidth, the acquisition range will be proportionally small; 2) it determines the maximum frequency variation in the input or the VCO that can be accommodated. In monolithic implementations, the VCO free-running frequency can vary substantially with temperature and process, thereby requiring a wide acquisition range even if the input frequency is tightly controlled.
FIG. 1
is a schematic block diagram of a PLL with aided frequency acquisition (prior art). Here, the system utilizes a frequency detector (FD) and a second low-pass filter, LPF
2
, whose output is added to that of LPF
1
. The FD produces an output having a dc value proportional to, and with the same polarity as &ohgr;
in
−&ohgr;
out
. If the difference between &ohgr;
in
and &ohgr;
out
is large, the PD output has a negligible dc component and the VCO is driven by the dc output of the FD with negative feedback, thereby moving &ohgr;
out
toward &ohgr;
in
. As |&ohgr;
in
−&ohgr;
out
| drops, the dc output of the FD decreases, whereas that of the PD increases. Thus, the frequency detection loop gradually relinquishes the acquisition to the phase-locked loop, becoming inactive when &ohgr;
in
−&ohgr;
out
=0.
It is important to note that in a frequency detection loop, the loop gain is relatively constant, independent of |&ohgr;
in
−&ohgr;
out
|, whereas in a simple phase-locked loop, it drops if |&ohgr;
in
−&ohgr;
out
| exceeds &ohgr;
LPF
. For this reason, aided acquisition using FDs can substantially increase the capture range.
For a VCO in a PLL, the following parameters are important. 1) Tuning range: i.e., the range between the minimum and maximum values of the VCO frequency. In this range, the variation of the output amplitude and jitter must be minimal. The tuning range must accommodate the PLL input frequency range as well as process- and temperature-induced variations in the VCO frequency range. The tuning range is typically at least ±20%w
FR
. 2) Jitter and phase noise: timing accuracy and spectral purity requirements in PLL applications impose an upper bound on the VCO jitter and phase noise. 3) Supply and substrate noise rejection: if integrated along with digital circuits, VCOs must be highly immune to supply and substrate noise. When used, a frequency divider can corrupt the VCO output by injecting noise into the common s

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