Phase-locked loop start-up techniques

Details Phase-locked loop start-up techniques Phase-locked loop start-up techniques

2008-04-25

2009-12-29

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331S018000, C331S025000, C455S260000

Reexamination Certificate

active

07639088

ABSTRACT:
Implementations feature systems and techniques for phase-locked loops (PLLs). In some aspects, implementations feature a system that has a PLL circuit including an oscillator and programmable reference frequency divider circuit or a programmable feedback frequency divider circuit. The PLL includes a control circuit to reduce a time required for a PLL settling time by programming a division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit to target the oscillator to operate outside of a system operating frequency range of the oscillator during start-up of PLL operations. The control circuit can program another division value into the programmable reference frequency divider circuit and/or the programmable feedback frequency divider circuit after stabilization of the variable oscillator.

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International Search Report, Application Serial No. PCT/US2008/062048, dated Jul. 21, 2008, 9 pages.

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