Phase locked loop reconfiguration

Details Phase locked loop reconfiguration Phase locked loop reconfiguration

2001-11-07

2003-09-16

Mis, David C. (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

C327S156000, C327S159000, C713S500000

Reexamination Certificate

active

06621353

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to phase locked loops and, more particularly, to reconfiguration of phase locked loops used for signal synchronization on integrated circuit chips.
2. Description of the Prior Art
Phase locked loops (PLLs) are a well-known type of circuit which are particularly useful for synchronization of signals when a signal frequency may change or drift and the frequency of a received signal must be closely tracked. Frequency modulated radio transmission receivers are a particularly well-known application for phase locked loops. Typically, a phase locked loop will contain a variable frequency (e.g. voltage controlled) oscillator as an internal clock; the output of which is compared with another signal and any phase discrepancy is fed back to the variable frequency oscillator as an error signal to adjust the frequency thereof. Thus, a local oscillator may be synchronized with an external clock or signal and allows the former to track frequency changes in the latter.
However, the frequency range over which tracking can be performed by a phase locked loop is often somewhat limited and the phase difference corresponding to an error signal of the magnitude necessary to drive a PLL oscillator to its variable frequency limits can be large. This phase difference can be quite significant and tolerable phase shifts may be limited in many applications, particularly digital communications. Therefore PLL designs must generally be designed for particular applications in consideration of the possible range of frequency variation, tracking accuracy in terms of resolution and response time) and allowable phase difference.
Relatively simple PLL circuits can be formed of relatively few elements if the operating parameters can be closely defined. However, to cover divergent frequency ranges, elements must often be substituted in PLL circuits or the PLL circuits otherwise reconfigured using switching elements that must be controlled with additional signals. Since PLLs operating over limited frequency ranges can be formed with relatively few circuit elements, they are often used for synchronization of digital signals in integrated circuits where signal propagation times may be quite variable but where frequency drift is generally limited.
For example, a data bus in an integrated circuit may comprise some of the longest signal paths in the chip design in order to traverse many of the operational portions or sections of the logic design which must be selectively connected during operation of the chip. Different operational sections of the integrated circuit will, of course be separated by different distances along the bus and different propagation times for signals between given sections of the integrated circuit will be evident. Synchronization is not particularly difficult in most cases for a bus connecting only portions of the same chip since only related clock frequencies derived from a single master oscillator for the chip are generally present. Therefore, a very simple PLL circuit is generally sufficient to lock a portion of the circuit to a signal it is to receive. Also, transmission over on-chip buses is predominantly in parallel and synchronization is principally for control of the data placed on the bus and the section of the chip which is to receive it.
The circumstance are quite different, however, for a bus used to interface with other chips or peripheral devices (e.g. input/output (I/O) buses) such as the peripheral component interconnect bus architecture (PCI) and the more recent version thereof referred to as PCI-X. In general, the signal paths are far longer and the number of signals which are propagated in parallel is often more limited: increasing the criticality of correct receipt of a sequence of changes of signal logic state over time. While transmission standards have been established, the bus architecture must usually accommodate several widely divergent frequencies or transmission bit rates in respective mode ranges. Therefore, complex and reconfigurable PLL circuits are necessary in such bus architectures.
Such a necessary capability, however, presents some practical difficulties for implementation. Devices for controlling bus architectures, such as PCI-X devices include registers to hold parameters of user defined configurations of the PLL. However, these registers must be clocked by the PLL in order to maintain synchronization with the PCI-X bus for storage of the PLL configuration parameters and glitches that result when a PLL is going in and out of a lock state cannot be tolerated even though these registers must be reset while the PLL is going through the reconfiguration process. Therefore, the normal configuration register such as are provided in a PCI/PCI-X device cannot be used as the exclusive means for holding reconfiguration data because these registers will be reset at the same time as the PLL when it is being reconfigured.
Use of an external source of the PLL configuration parameters is not practical for different configurations for each of even a small plurality of mode ranges since the number of configurations, if mapped to device package pins would increase the required size of the device package as well as increasing the complexity of making connections to the device. The only alternative at the present state of the art is to use an additional service processor to access the PLL through an IEEE 1149.1 interface, which may not be available and, in any case, would greatly increase the cost of implementation of the bus.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a technique and inexpensive apparatus in a device for implementation of a bus architecture which allows reconfiguration of a PLL to accommodate a plurality of bus mode ranges through normal bus transactions.
It is another object of the invention to provide for control of a PLL over a plurality of operational mode ranges without requiring external direct control signal connections.
It is a further object of the invention to provide control of a PLL using circuitry which is controlled by the PLL.
In order to accomplish these and other objects of the invention, a combination of elements is provided including a clock source including a reconfigurable phase locked loop, a state machine providing a timed sequence of states, and at least one register for capturing reconfiguration parameters and loading the captured reconfiguration parameters into the reconfigurable phase locked loop responsive to the state machine.
In accordance with another aspect of the invention, a method for reconfiguring a phase locked loop is provided including steps of capturing reconfiguration parameters in a register means, and transferring the captured reconfiguration parameters to the phase locked loop, wherein the capturing step and the transferring step are performed in sequence responsive to a sequence of steps of a state machine and independently of clocking signals produced by the phase locked loop.


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