Phase locked loop providing fast tuning for large frequency chan

Details Phase locked loop providing fast tuning for large frequency chan Phase locked loop providing fast tuning for large frequency chan

1995-07-20

1997-11-11

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

331 25, H03L 7085

Patent

active

056868669

ABSTRACT:
A more rapid charging of an integrating capacitor of a PLL is provided when large frequency changes are desired. In one embodiment, the phase locked loop (PLL) circuit sinks or sources current to charge or discharge the integrating capacitor. A threshold voltage proportional to a current through the capacitor turns on an augmenting circuit which sinks or sources more current of the proper polarity to the integrating capacitor from an external source until a PLL lock is achieved. Once the lock is achieved, if a small correction current is required by the PLL, the small correction current is below a threshold required to actuate the augmenting circuit, and the PLL loop behaves in the usual manner as if the augmenting circuit were not present. In another embodiment, the integrating capacitor is reduced in value by switchably connecting a second capacitor in series with the integrating capacitor so that the total reduced capacitance of reduced value can be charged more quickly.

REFERENCES:
patent: 3694776 (1972-09-01), Linder
patent: 4377728 (1983-03-01), Hilbert
patent: 4890072 (1989-12-01), Espe et al.
patent: 5059979 (1991-10-01), Micic et al.
patent: 5153530 (1992-10-01), Takagi et al.
patent: 5220294 (1993-06-01), Ichikawa
patent: 5386437 (1995-01-01), Yasuda
Digital Fast Acquisition Method for Phase-Lock Loops, By R.C. Den Dulk, GB Electronics Letters, Aug. 18, 1988, vol. 24, No. 17, pp.1079-1080.

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