Phase locked loop (PLL) frequency synthesizer and method

Details Phase locked loop (PLL) frequency synthesizer and method Phase locked loop (PLL) frequency synthesizer and method

2005-07-26

2005-07-26

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural oscillators controlled

C331S016000, C331S017000, C331S018000, C331S068000

Reexamination Certificate

active

06922110

ABSTRACT:
A phase locked loop (PLL) frequency synthesizer generates a high frequency signal by generating an output signal from a voltage controlled oscillator of a primary phase locked loop (PLL) circuit. The voltage controlled oscillator output is programmably divided with a reference signal output at a divide ratio such that the outputs are equal to a common phase comparison frequency. An external reference signal used for the primary phase locked loop circuit is isolated by generating a voltage controlled, clean reference signal and filtering and synchronizing the clean reference signal with the external reference signal within a secondary phase locked loop circuit to produce the reference signal output to the primary phase locked loop circuit.

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Patent Abstracts of Japan, vol. 2000, No. 19, Jun. 5, 2001 and JP 2001 053607A (Fujitsu Ltd.), Feb. 23, 2001, one page.

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