Phase locked loop (PLL) for integrated circuits

Details Phase locked loop (PLL) for integrated circuits Phase locked loop (PLL) for integrated circuits

2005-05-03

2005-05-03

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S156000

Reexamination Certificate

active

06888385

ABSTRACT:
An improved Phase Locked Loop (PLL) for digital integrated circuits. A characteristic of this PLL is that the Voltage Controlled Oscillator (VCO) output is fed to the phase and frequency detector (PFD) input through a clock-tree replica providing a delay equal to the routed clock tree. “This enables the PLL to maintain the proper phase even during a sleep mode of operation.”

REFERENCES:
patent: 6023180 (2000-02-01), Schmidt
patent: 6326812 (2001-12-01), Jefferson
patent: 6718477 (2004-04-01), Plants et al.
patent: 6762629 (2004-07-01), Tam et al.

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