Phase-locked loop (PLL) circuit containing a phase detector for

Details Phase-locked loop (PLL) circuit containing a phase detector for Phase-locked loop (PLL) circuit containing a phase detector for

1998-01-28

2000-06-06

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327 9, 327159, 375376, H04L 704

Patent

active

060723440

ABSTRACT:
A parallel sampling receiver is disclosed that utilizes a sampled binary phase detector (SBPD) to achieve byte alignment. A parallel sampling receiver utilizes five parallel sampled phase detectors to sample incoming data and an additional edge-detecting sampled binary phase detector (SBPD) operating as a phase detector for sampling the incoming data signal between two data bits, such as data bits D.sub.4 and D.sub.5. The sampled binary phase detector (SBPD) should be either high or low if there is a binary transition from high to low between data bits D.sub.4 and D.sub.5, indicating whether the sampling is being done just before or just after the falling edge, respectively. Byte alignment is provided by the parallel sampling receiver. The edge-detecting sampled binary phase detector (SBPD) will automatically perform byte alignment if a preamble in the frame header consists, for example, of consecutive 11001 bytes (in an illustrative 5 bit implementation) and the edge-detecting sampled binary phase detector (SBPD) is made to lock onto a positive edge. The predefined preamble sequence should contain only one positive edge, positioned at the location of the edge-detecting sampled binary phase detector (SBPD).

REFERENCES:
patent: 5367542 (1994-11-01), Guo
patent: 5739762 (1998-04-01), Kuramatsu et al.

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