Phase-locked loop (PLL) circuit and method

Details Phase-locked loop (PLL) circuit and method Phase-locked loop (PLL) circuit and method

2011-01-11

2011-01-11

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S157000, C327S159000

Reexamination Certificate

active

07868670

ABSTRACT:
A phase-locked loop (PLL) circuit includes a reference clock divider with a reference clock input, a phase-frequency detector, a charge pump, a loop filter, a voltage controlled oscillator and a feedback divider. A method of operating the PLL circuit comprises the steps of detecting a failure of a reference clock applied to the reference clock input, disabling the charge pump upon detection of a reference clock failure, monitoring the reference clock to detect restoration of a regular reference clock, upon detection of a regular reference clock, detecting occurrence of the next pulse from the feedback divider, and enabling the charge pump upon detection of the next pulse from the feedback divider.

REFERENCES:
patent: 6304147 (2001-10-01), Bonnot
patent: 6414535 (2002-07-01), Ooishi
patent: 6624675 (2003-09-01), Neron
patent: 6661254 (2003-12-01), Agrawal et al.
patent: 6956416 (2005-10-01), Wilson et al.
patent: 7323946 (2008-01-01), Seefeldt et al.
patent: 28 56 211 (1978-12-01), None
patent: 3-240318 (1991-10-01), None

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