Phase locked loop (PLL) circuit

Details Phase locked loop (PLL) circuit Phase locked loop (PLL) circuit

1998-12-09

2000-12-19

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327147, 327157, H03L 706

Patent

active

061631841

ABSTRACT:
A phase locked loop (PLL) includes a programmable frequency multiplier section and a programmable divide-by-N network connected in a feedback loop between an output and an input of the frequency multiplier. The frequency multiplier section includes programmable circuitry which is programmed to vary as a function of N to render the bandwidth of the PLL independent of the divider ratio "N". The frequency multiplier includes a charge pump circuit, a filter circuit and a voltage controlled oscillator (VCO) circuit with the programmable circuitry being formed in one of these circuits to render the bandwidth of the PLL independent of the divider ratio, whereby the bandwidth is increased and the jitter at the PLL output is decreased.

REFERENCES:
patent: 5367269 (1994-11-01), Yanagidaira et al.
patent: 5420545 (1995-05-01), Davis et al.

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