Phase locked loop lock condition detector

Details Phase locked loop lock condition detector Phase locked loop lock condition detector

1997-12-22

1999-10-19

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 25, 331DIG2, H03L 7095

Patent

active

059695765

ABSTRACT:
A lock detector for a phase locked loop circuit, wherein an oscillator is controlled by a control signal produced by comparing the output signal of the oscillator to a reference signal. The lock detector samples the control signal, examines a plurality of samples according to criteria associated with a prescribed lock condition between the reference signal and the oscillator output signal, and generates a lock signal indicative of the lock condition being met if the samples satisfy the criteria. In a favorable embodiment, the lock detector forms a first group of samples sampled at a rate controlled by the reference signal and a second group of samples sampled at a rate controlled by the oscillator output signal. The samples are stored and shifted at the respective rates in respective shift registers. The contents of each stage of the shift registers are then examined according to a logic function. In an embodiment, the control signal includes first and second commands and is subjected to an initial logic function whose output is sampled by the shift registers.

REFERENCES:
patent: 4806878 (1989-02-01), Cowley
patent: 5189379 (1993-02-01), Saito et al.
patent: 5530383 (1996-06-01), May
Kaenel et al, "A 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for Microprocessor Clock Generation", IEEE Journal of Solid State Circuits, Nov. 1996, vol. 31, No. 11, pp. 1715-1722.

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