Phase-locked loop integrated circuits that support clock...

Details Phase-locked loop integrated circuits that support clock... Phase-locked loop integrated circuits that support clock...

2005-08-02

2005-08-02

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S156000

Reexamination Certificate

active

06924677

ABSTRACT:
PLL integrated circuits include a charge pump having first and second input terminals that are configured to receive UP and DOWN control signals, respectively. A phase detector is also provided. The phase detector is configured to generate the UP and DOWN control signals at active levels during a dead zone compensation time interval using a control circuit that is responsive to at least one signal generated by the charge pump. The control circuit is further configured to support reference clock signal and/or feedback clock signal updates to the phase detector during the dead zone compensation time interval.

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Notice to Submit Response, Japanese Application No. 10-2003-0015864, Jan. 26, 2005.

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