Phase-locked loop including sampling phase detector and...

Details Phase-locked loop including sampling phase detector and... Phase-locked loop including sampling phase detector and...

2008-03-07

2010-06-15

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S156000, C327S163000, C375S375000, C375S376000

Reexamination Certificate

active

07737743

ABSTRACT:
Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in accordance with the reference signal and a frequency detector detects the output signal frequency in accordance with the reference signal.

REFERENCES:
patent: 6055286 (2000-04-01), Wu et al.
patent: 6081572 (2000-06-01), Filip
patent: 2008/0218274 (2008-09-01), Clementi
Anand et al., “A CMOS Clock Recovery Circuit for 2.5-Gb/s NRZ Data”, IEEE Journal of Solid-State Circuits, vol. 36, No. 3, Mar. 2001, pp. 432-439.
Maulik et al., “A 150 MHz-400MHz DLL-Based Programmable Clock Multiplier with -70dBc Reference Spur in 0.18um CMOS”, IEEE 2006, CICC, pp. 757-760.
Desgrez et al., “A New MMIC Sampling Phase Detector Design for Space Applications”, IEEE Journal of Solid State-Circuits, vol. 38, No. 9, Sep. 2003, pp. 1438-1442.

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