Phase locked loop including a sampling circuit for reducing spur

Details Phase locked loop including a sampling circuit for reducing spur Phase locked loop including a sampling circuit for reducing spur

1996-11-18

1999-07-06

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

With intermittent comparison controls

331 17, 331 25, 331DIG2, H03L 7085

Patent

active

059202335

ABSTRACT:
An apparatus and method for reducing spurious sidebands in the tuning signal of phase locked loop frequency synthesizers and phase locked loops is disclosed. The frequency synthesizer includes an oscillator, a divider, a difference circuit and a sampling circuit. The oscillator produces a variable frequency oscillator signal in response to an applied tuning signal. The divider divides the variable frequency oscillator signal by a division factor to produce a reduced frequency signal. The difference circuit receives the reduced frequency signal to produce a difference signal corresponding to the phase difference between the reference signal and the reduced frequency signal. The sampling circuit intermittently samples the difference signal in response to a timing signal to produce a tuning signal which approaches a DC characteristic. The tuning signal serves to adjust the oscillator frequency in a direction to diminish phase differences in the reference signal and the reduced frequency signal. In another aspect of the invention, a PLL is disclosed with the sampling circuitry for intermittently sampling the difference signal in response to a timing signal.

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Roland E. Best, Phase-Locked Loops Theory, Design and Applications, The Classical Digital PLL (DPLL), 1993, pp. 93-104 McGraw-Hill, U.S.A.
William F. Egan, Frequency Synthesis By Phase Lock, "Phase Detectors", 1990, pp. 98-123, Robert E. Krieger Publishing Co., Malabar, Fl.

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