Phase-locked loop having temperature-compensated bandwidth...

Details Phase-locked loop having temperature-compensated bandwidth... Phase-locked loop having temperature-compensated bandwidth...

1999-05-19

2001-04-03

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular frequency control means

C331S008000, C331S017000, C331S018000, C331S025000

Reexamination Certificate

active

06211743

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to phase-locked loops and, more particularly, relates to a phase-locked loop having a loop bandwidth that is compensated for temperature variations.
BACKGROUND OF THE INVENTION
Many electrical and computer applications and components have critical timing requirements that compel generation of periodic clock waveforms that are precisely synchronized with a reference clock waveform. A phase-locked loop (“PLL”) is one type of circuit that is widely used to provide an output signal having a precisely controlled frequency that is synchronous with the frequency of a received or input signal. Wireless communication devices, frequency synthesizers, multipliers and dividers, single and multiple clock generators, and clock recovery circuits are but a few examples of the manifold implementations of PLLs.
Frequency synthesis is a particularly common technique used to generate a high frequency clock from a lower frequency reference clock. In microprocessors, for example, an on-chip PLL can multiply the frequency of a low frequency reference (off-chip) clock, typically in the range of 1 to 4 MHz, to generate a high frequency output clock, typically in the range of 10 to over 200 MHz, that is precisely synchronized with the lower frequency reference clock. Another common use of PLLs is recovery of digital data from serial data streams by locking a local clock signal onto the phase and frequency of the data transitions. The local clock signal is then used to clock a flip-flop or latch receiving input from the serial data stream.
FIG. 1
is a block diagram of a typical PLL
10
. PLL
10
comprises phase/frequency detector
12
, charge pump
14
, loop filter
16
, oscillator
18
and frequency divider
20
. PLL
10
receives a reference clock signal CLK
REF
having a frequency F
REF
and generates an output clock signal CLK
OUT
having a frequency F
OUT
that is synchronized with the reference clock signal in phase. The output clock frequency may be an integer (N) multiple of the reference frequency; with the parameter N set by frequency divider
20
. Hence, for each reference signal period, there are N output signal periods or cycles.
Phase detector
12
receives on its input terminals two clock signals CLK
REF
and CLK
OUT
* (CLK
OUT
, with its frequency F
OUT
divided down by frequency divider
20
). In a conventional arrangement, detector
12
is a rising edge detector that compares the rising edges of the two clock signals. Based on this comparison, detector
12
generates one of three states. If the phases of the two signals are aligned, the loop is “locked”. Neither the UP nor the DOWN signal is asserted and oscillator
18
continues to oscillate at the same frequency. If CLK
REF
leads CLK
OUT
*, than oscillator
18
is oscillating too slowly and detector
12
outputs an UP signal proportional to the phase difference between CLK
REF
and CLK
OUT
*. Conversely, if CLK
REF
lags CLK
OUT
*, than oscillator
18
is oscillating too quickly and detector
12
outputs a DOWN signal proportional to the phase difference between CLK
REF
and CLK
OUT
*. The UP and DOWN signals typically take the form of pulses having a width or duration corresponding to the timing difference between the rising edges of the reference and output clock signals. They have a complementary relationship such that neither is asserted at the same time and, if one is asserted, the other is not asserted.
Charge pump
14
generates a current I
CP
that controls the oscillation frequency F
OUT
of oscillator
18
. I
CP
is dependent on the signal output by phase detector
12
. If charge pump
14
receives an UP signal from detector
12
, indicating that CLK
REF
leads CLK
OUT
*, I
CP
is increased. If charge pump
14
receives a DOWN signal from detector
12
, indicating that CLK
REF
lags CLK
OUT
*, I
CP
is decreased. If neither an UP nor a DOWN signal is received, indicating that the clock signals are aligned, charge pump
14
does not adjust I
CP
.
Loop filter
16
is positioned between charge pump
14
and oscillator
18
. Application of the charge pump output current I
CP
to loop filter
16
develops a voltage V
LF
at the output of filter
16
. Filter
16
also removes out-of-band, interfering signals. V
LF
is then applied to oscillator
18
to control the frequency F
OUT
of the output clock signal. A common configuration for a loop filter in a PLL is a simple single-pole, low-pass filter that can be realized with a single resistor and capacitor.
Oscillator
18
generates an oscillating output signal CLK
OUT
having a frequency F
OUT
proportional to the voltage V
LF
applied to oscillator
18
. Conventional oscillators typically oscillate about a specific center frequency and have a relatively narrow frequency range or bandwidth. When CLK
REF
leads CLK
OUT
*, charge pump
14
increases I
CP
to develop a greater V
LF
at the output of loop filter
16
which, in turn, causes oscillator
18
to increase F
OUT
. Conversely, when CLK
REF
lags CLK
OUT
*, charge pump
14
decreases I
CP
to develop a lesser V
LF
at the output of loop filter
16
which, in turn, causes oscillator
18
to decrease F
OUT
. When CLK
REF
and CLK
OUT
* are aligned, V
LF
is not adjusted, and F
OUT
is kept constant. In this state, PLL
10
is in a “locked” condition.
The output clock signal is also looped back through (in some applications) frequency divider
20
. The resultant output CLK
OUT
* is provided to phase/frequency detector
12
to facilitate the phase-locked loop operation. Frequency divider
20
divides F
OUT
by the multiplication factor N to obtain a divided clock. Divider
20
may be implemented using counters, shift registers, or through other methods familiar to those of skill in the art. Thus, PLL
10
compares the reference clock phase to the divided clock phase and eliminates any detected phase difference between the two by adjusting the frequency of the output clock.
In many applications, it is desirable and advantageous to integrate all of the components of a phase-locked loop on a semiconductor chip. On-chip phase-locked loops are often implemented using CMOS technology. Due to the high temperature coefficients displayed by some of the integrated components, however, it is difficult to maintain a constant loop bandwidth over temperature variations. This is especially problematic in digital CMOS, which requires the use of integrated circuitry components having particularly high temperature coefficients, such as well resistors.
In view of the above, there is a need for a phase-locked loop that demonstrates a stable bandwidth in relation to temperature variations.
SUMMARY OF THE INVENTION
In accordance with the purpose of the invention as broadly described herein, there is provided a phase-locked loop that demonstrates a stable and substantially constant bandwidth in relation to temperature variations.
In one embodiment of the present invention, a phase-locked loop includes a phase/frequency detector that compares a reference clock with an output clock and generates an appropriate charge pump control voltage. A charge pump coupled to the phase/frequency detector generates a loop filter control current from the charge pump control voltage. A loop filter coupled to the charge pump applies the loop filter control current to a first temperature-variable resistor to generate a loop filter voltage. An oscillator coupled to the loop filter includes a voltage-to-current converter that receives the loop filter voltage and generates a reference current by applying the loop filter voltage across a second temperature-variable resistor. The oscillator also includes a current-controlled oscillator that generates the output clock based on the value of the reference current. The oscillator has a gain that is inversely related to the resistance of the second resistor. Accordingly, temperature-induced variations of the resistances of the first and second resistors do not substantially affect the loop bandwidth. A feedback circuit is coupled between the oscillator and the phase

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