Phase-locked loop having phase detector error signal...

Details Phase-locked loop having phase detector error signal... Phase-locked loop having phase detector error signal...

2002-09-13

2004-08-24

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Tuning compensation

C331S017000, C331S011000, C327S156000, C327S157000, C327S159000, C375S375000, C375S376000

Reexamination Certificate

active

06781469

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to phase-locked loop, and more specifically to a phase-locked loop employing error signal reshaping and an associated method.
2. Description of the Prior Art
Phase-locked loops are widely used in digital electronics, signal telemetry, and communications applications. Within these applications, phase-locked loops are extensively used for clock distribution and recovery, and demodulation of data.
Phase locked-loops operate by producing an oscillator frequency to match a frequency of an input signal. Consider a basic phase-locked loop
10
illustrated in FIG.
1
. The phase-locked loop
10
includes a phase detector
12
that compares the phase of an input signal S
1
with the phase of a feedback signal S
2
. The phase detector
12
generates a phase error signal associated with the difference between the phases of the signals S
1
and S
2
. A frequency detector
13
is also provided to compare the frequency of the input signal S
1
with the frequency of the feedback signal S
2
and generate a frequency difference signal. Typically, the phase error signal is a pulsed signal where the width of a pulse describes the magnitude of the phase difference of the signals S
1
and S
2
.
Further provided is a charge pump
14
that generates an amount of charge equivalent to the phase error signal or the frequency difference signal. The charge generated by the charge pump
14
causes a filter
16
to output a signal S
3
to a voltage-controlled oscillator (VCO)
18
. The filter
16
may be a loop filter or a low pass filter for example. The VCO
18
generates a periodic signal according to the output signal S
3
. A feedback frequency divider
20
divides the output of the VCO
18
and outputs the feedback signal S
2
to the phase detector
12
. Thus, a feedback loop is formed and the phase-locked loop
10
tends to lock the feedback signal S
2
with the input signal S
1
. Output from the phase-locked loop
10
can be taken as the output signal S
3
or as the feedback signal S
2
depending on the application.
Numerous improvements have been made to the basic phase-locked loop
10
with respect to different fields of application. A particular design that offers improved operation at high frequencies is taught by Bailey et al. in U.S. Pat. No. 6,040,742, which is included herein by reference. An example of such a phase-locked loop is illustrated in
FIG. 2. A
phase locked-loop
30
includes a phase detector
32
, a charge pump
34
, a filter
36
, and a VCO
38
. The phase-locked loop
30
is similar to the phase-locked loop
10
except for the charge pump
34
and its interaction with the phase detector
32
.
Operation of the phase-locked loop
30
is only briefly described as follows. The charge pump
34
has an UP current source that generates a DC UP current I
UP
and a DOWN current source that generates a DC DOWN current I
DN
that is dynamically controlled based on DOWN signals from the phase detector
32
. The magnitudes of the UP current I
UP
and the DOWN current I
DN
are controlled by the voltages V
REF
and V
C
respectively and by a bias voltage V
DD
. The charge pump
34
outputs a current I
CP
that has the constant UP component I
UP
that is decreased by the DOWN component I
DN
when the phase detector
32
outputs a DOWN pulse signal. The DOWN pulse signal output by the phase detector
32
describes the phase difference between the phase &thgr;
IN
of the input signal F
IN
and the phase &thgr;
OUT
of the output signal F
OUT
. The charge pump
34
outputs current I
CP
controlling the filter
36
to output a voltage V
LF
that results in locking of the phase &thgr;
IN
of the signal F
IN
and the phase &thgr;
OUT
of the signal F
OUT
. Because of differences in mobility of holes and electrons in CMOS circuitry, the phase-locked loop
30
has quicker response than the basic phase-locked loop
10
.
Nevertheless, prior art phase-locked loops can still suffer from poor response. More specifically, phase-locked loops using frequency detectors in conjunction with phase detectors can have ranges where a given frequency cannot be properly locked.
SUMMARY OF INVENTION
It is therefore a primary objective of the present invention to provide a phase-locked loop having a signal reshaper for providing an increased responsiveness and for solving the problems of the prior art.
Briefly summarized, a preferred embodiment of the present invention includes a phase-locked loop having a signal reshaper connected between a phase detector and and a charge pump. The signal reshaper can reshape the phase error signal and outputs a reshaped or unreshaped phase error signal to the charge pump. The unreshaped phase error signal causes the charge pump to output a charge pump signal that changes the frequency of a feedback signal to match the frequency of an input signal, and the reshaped phase error signal causes the charge pump to output a charge pump signal that synchronizes an output signal with a target frequency.
According to a preferred embodiment of the present invention, when the frequency of the output signal is in a lower range that is lower than the target frequency, the signal reshaper reshapes the phase error signal to increase the frequency of the output signal out of the lower range. Furthermore, when the frequency of the output signal is in an upper range that is above the target frequency, the signal reshaper reshapes the phase error signal to decrease the frequency of the output signal out of the upper range.
According to a preferred embodiment of the present invention, the lower range and the upper range are frequency ranges where the unreshaped phase error signal is incapable of synchronizing the output signal with the target frequency.
According to a preferred embodiment of the present invention, the signal reshaper is a pulse reshaper and the phase error signal comprises up pulses and down pulses, and the pulse reshaper lengthens or shortens a period of a pulse of the phase error signal to reshape the phase error signal.
According to a preferred embodiment of the present invention, a controller can control the charge pump to increase or decrease an amplitude of a pulse to reshape the phase error signal.
It is an advantage of the present invention that the pulse reshaper and charge pump reshape pulses of the phase error signal to quickly synchronize the output signal with the target frequency.
It is a further advantage of the present invention the pulse reshaping provided by the pulse reshaper and the charge pump substantially reduces ranges of output signal frequencies that cannot be locked properly.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.


REFERENCES:
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patent: 5825210 (1998-10-01), Oh
patent: 5889828 (1999-03-01), Miyashita et al.
patent: 6040742 (2000-03-01), Bailey et al.
patent: 6154071 (2000-11-01), Nogawa
patent: 6285219 (2001-09-01), Pauls
patent: 6326826 (2001-12-01), Lee et al.
patent: 6525612 (2003-02-01), Aoki
patent: 2001/0030560 (2001-10-01), Neron
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