Phase locked loop having memory

Details Phase locked loop having memory Phase locked loop having memory

1997-06-18

1999-06-08

Pham, Chi H.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

527158, 527147, 375576, 375375, 370518, H03L 706

Patent

active

059107405

ABSTRACT:
A phase locked loop that enables highly precise tracking and phase locking of a synthesized clock signal to a reference clock signal. The phase locked loop has a memory that enables highly precise tracking and phase locking of a synthesized clock signal to its reference clock signal. The phase locked loop predicts the exact delay setting required for a frequency match, so that over-shoots and under-shoots around a desired frequency are minimized, and correction sizes are bounded to a relatively small region in the proximity of the desired frequency. The phase locked loop uses a dynamically programmable digital delay line to implement a variable frequency oscillator. The programmable delay line is used to produce a desired synthesized clock period. The phase locked loop provides an oscillator source whose period is determined by a delay derived from a clock distribution circuit plus a delay derived from the programmable delay line. A phase detector provides phase relationship information to control logic that indicates whether the synthesized clock signal leads or lags the reference clock signal. Divide by K logic provides every K.sup.th synthesized clock edge to the phase detector which corresponds to the occurrence of the reference clock edge. The control logic implements novel methods to control the delay associated with each half clock period in a way that minimizes phase error. Optional reference clock insertion capability provided by a multiplexer enables perfect phase alignment to be achieved each time a reference clock edge occurs.

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