Phase locked loop having low-frequency jitter compensation

Details Phase locked loop having low-frequency jitter compensation Phase locked loop having low-frequency jitter compensation

1990-12-03

1991-07-30

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 17, 375120, H03L 7093

Patent

active

050362941

ABSTRACT:
A phase locked loop circuit generates an output clock that is in phase with a reference clock and is frequency jitter compensated at lower frequencies by translating intrinsic jitter frequency from low frequency to a predetermined range of higher frequencies. The phase locked loop circuit utilizes dithering circuitry to control a switched capacitor network in order to reduce the magnitude of the frequency jitter at lower frequencies. A phase detector and a loop filter of the phase locked loop circuit are implemented using digital circuitry. An oscillator of the phase locked loop is an analog oscillator which is digitally controlled and includes the switched capacitor network. Quantization error in the output clock is minimized by switching an LSB weighted capacitor in the oscillator at a frequency established by the dithering circuitry.

REFERENCES:
patent: 4941156 (1989-03-01), Stern et al.
patent: 4942370 (1990-07-01), Shigemori
patent: 4942371 (1990-07-01), Kashiwaba et al.

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