Phase-locked loop having loop gain and frequency response...

Details Phase-locked loop having loop gain and frequency response... Phase-locked loop having loop gain and frequency response...

2003-04-08

2004-05-04

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S147000

Reexamination Certificate

active

06731145

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to phase-locked loops, and particularly relates to improving the performance of a phase-locked loop using a calibration circuit.
BACKGROUND OF THE INVENTION
Frequency synthesizers are commonly used to generate radio frequency (RF) signals for use in communication systems. A common form of frequency synthesizer is the charge pump phase-locked loop (PLL).
In modern portable communication systems, it is desirable to integrate as many components and devices as possible into low-cost integrated circuits (ICs), thereby reducing the material and manufacturing costs associated with discrete components. Examples of integrated frequency synthesizers can be found in most microprocessors and in many low-performance transceivers. However, the use of integrated frequency synthesizers in high-performance cellular or wireless LAN communication systems has been limited; for example, the voltage-controlled oscillator (VCO) and loop filter are typically external components, while the remaining loop components are integrated on a single IC. The use of a high reference frequency (F
R
), such as afforded by communications systems with wide channel spacings or fractional-N frequency synthesis, reduces the contribution of charge pump and loop filter noise components to the output spectrum to the point where full integration becomes possible.
The use of fractional-N synthesis also enables digital modulation for phase or frequency based systems. Modern communication systems, such as the Global System for Mobile Communication (GSM) cellular telephone system, impose strict requirements on the locktime and noise performance of the transmitted signal, and on the signals used for mixing in the receiver. For example, the transmit locktime must typically be under 250 &mgr;s to settle the VCO to under 100 Hz error, and the transmitted phase noise must be under 113 dBc/Hz at 400 kHz offset. If the loop bandwidth is too wide, the noise performance specification may not be met, and if the loop bandwidth is too narrow, the locktime specification may not be met. In addition, the phase error of the transmitted signal must remain small (under 5 degrees root-mean-square in the GSM system). Variations in loop gain and bandwidth can degrade the performance of fractional-N based transmit systems in which a predistortion filter is used to compensate for the rolloff of the loop response.
Thus, the variations inherent to transistor, resistor, and capacitor devices in low cost semiconductor processes leads to unacceptable variations in the loop bandwidth and gain, degrading the locktime, noise, and phase error of the frequency synthesizer.
Hence, there remains a need for a calibration system to cancel out the undesirable process and environmental variations that degrade the performance of integrated frequency synthesizers while providing a desired, arbitrary level of accuracy with minimal overhead in terms of device area and calibration time. Ideally this calibration system should function automatically, with little or no user intervention, and the calibration should complete rapidly enough to be performed each time the frequency synthesizer is enabled.
SUMMARY OF THE INVENTION
The invention provides an apparatus for calibrating both the pole/zero locations and the gain of a charge pump phase-locked loop's (PLL) frequency response with one calibration operation. In one embodiment, the calibration is performed using a bandgap voltage reference and a stable frequency reference in order to measure a slew rate of a reference capacitor, wherein the slew rate is defined as a current-to-capacitance ratio (I/C). The RC time constant (RC) of a loop filter is then adjusted based on the measured slew rate by adjusting the capacitance values of variable capacitor arrays in the loop filter, thereby calibrating the pole and zero locations of the PLL, which depend on the RC product. A charge pump reference current required by a charge pump in the PLL is proportional to a timing current used to measure the slew rate, wherein both the charge pump reference current and the timing current are proportional to a reference current, thereby correlating the RC time constant and the slew rate. Therefore, the adjustment of the capacitance values of the loop filter calibrates the slew rate as well as the RC time constant, wherein the slew rate represents a portion of the loop gain of the PLL. In one embodiment, a frequency synthesizer including the calibration circuit is implemented in a single integrated circuit (IC).


REFERENCES:
patent: 4206398 (1980-06-01), Janning
patent: 5382923 (1995-01-01), Shimada et al.
patent: 6046646 (2000-04-01), Lo et al.
patent: 6542040 (2003-04-01), Lesea

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