Phase locked loop having integration gain reduction

Details Phase locked loop having integration gain reduction Phase locked loop having integration gain reduction

1995-12-08

1998-06-16

Tran, Toan

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

331 1A, 327155, H03L 706

Patent

active

057677131

ABSTRACT:
A non-linear integrated phase locked loop circuit includes a phase detector for receiving a data signal and a clock pulse and for outputting a pump-up signal and a pump-down signal, a pulse divider connected to the phase detector for receiving the pump-up signal and the pump-down signal and producing a first output at predetermined multiples of the pump-up signal and a second output at predetermined multiples of the pump-down signal. A pulsed filter or integrator is connected to the pulse divider for receiving the first output and the second output and providing a frequency control signal for a voltage controlled oscillator. A three state amplifier is connected to the phase detector for receiving the pump-up signal and the pump-down signal and providing a phase control signal for a voltage controlled oscillator. The voltage controlled oscillator is connected to the pulsed filter and the amplifier for receiving the frequency control signal and the phase control signal and producing a corresponding output. In a second embodiment, the phase detector outputs a polarity signal and an enable signal along with a pump-up signal and a pump-down signal. The pulse divider is a pulse incrementor/decrementor connected to the phase detector for receiving the polarity signal and the enable signal and producing a first output at a predetermined increment of the polarity signal and a second output at a predetermined decrement of the enable signal.

REFERENCES:
patent: 4504799 (1985-03-01), Elmis et al.
patent: 4528521 (1985-07-01), Grimes
patent: 4577163 (1986-03-01), Culp
patent: 5075640 (1991-12-01), Miyazawa

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