Phase locked loop having infinite gain at zero phase error

Details Phase locked loop having infinite gain at zero phase error Phase locked loop having infinite gain at zero phase error

1981-10-26

1984-07-10

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 17, 331 25, 331 36C, 331177V, 331DIG3, H03B 536, H03L 708

Patent

active

044595581

ABSTRACT:
A phase-locked loop for use in the common T1 systems. The phase relationship of the clock pulse output of a voltage controlled oscillator is determined with respect to an incoming data pulse train. If the clock signal leads the data signal, an error signal of a first polarity is applied to an integrator whose output is provided to the VCO to reduce the frequency of the clock pulse. If the clock signal lags the data signal, an error signal of a second polarity is applied to the integrator whose output is provided to the VCO to increase the frequency of the clock pulse. The logic of the circuitry is such that the output of the integrator is always either increasing or decreasing, even if there is zero phase error between the clock pulse and data pulse (i.e. the loop has infinite gain for zero error). The integrator continues to integrate in a first direction until the frequency of the clock pulses is adjusted so far that the lead is changed to a lag or vice-versa, with respect to the next data pulse.

REFERENCES:
patent: 3503003 (1970-03-01), Grobert
patent: 3560879 (1971-02-01), Fuchs
patent: 3670255 (1972-06-01), DeNicolay et al.
patent: 3805180 (1974-04-01), Widmer
patent: 4055814 (1977-10-01), Abraham et al.

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