Phase-locked loop having improved locking times and a method of

Details Phase-locked loop having improved locking times and a method of Phase-locked loop having improved locking times and a method of

1997-10-31

1999-09-28

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327159, 331 16, H03L 700

Patent

active

059594780

ABSTRACT:
An electronic device is delineated comprising, in combination, a Phased Lock Loop (PLL) having a charge pump, and a mixed signal circuit coupled in parallel to the charge pump. The mixed signal circuit includes analog circuitry for adding charge to and removing charge from capacitors in a Low Pass Filer (LPF) of the PLL. The mixed signal circuit also includes digital circuitry for controlling the initiation and termination of both the charging and discharging operations carried on by the analog portion of the mixed signal circuit. Upon a significant change in system frequency, the mixed signal circuit first fully discharges and then rapidly charges the capacitors in the LPF in a manner which results in a significant reduction in PLL locking time.

REFERENCES:
patent: 5170130 (1992-12-01), Ichihara
patent: 5220294 (1993-06-01), Ichikawa
patent: 5347233 (1994-09-01), Ishibashi et al.
patent: 5534823 (1996-07-01), Kondou
patent: 5677648 (1997-10-01), Jones

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