Oscillators – Automatic frequency stabilization using a phase or frequency... – Afc with logic elements
Reexamination Certificate
1999-12-23
2001-09-04
Grimm, Siegfried H. (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Afc with logic elements
C331S017000, C331S025000, C331S014000
Reexamination Certificate
active
06285260
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a phase-locked loop (PLL) circuit.
2. Description of the Prior Art
A PLL frequency synthesizer, known as a PLL circuit, which is currently available in mobile communications and other applications is shown in
FIG. 4. A
counter
42
divides a frequency of an output signal of a reference signal source
41
to produce an output signal indicative of a divided frequency signal of the reference signal source
41
. Another counter
44
divides a frequency of an output signal of a voltage-controlled oscillator (VCO) circuit
43
to produce an output signal indicative of a divided frequency signal of the output signal from the voltage-controlled oscillator (VCO) circuit
43
. A phase comparator circuit
45
compares these two output signals and produces output signals from its terminals UP and DN, respectively. These output signals have pulse widths corresponding to the amount of lag or lead of the phase of the output signal FV from the counter
44
with respect to the output signal FR from the counter
42
. A charge pump
46
charges or discharges capacitive elements (not shown) in response to the output signals appearing at the terminals UP and DN. The charging current from the charge pump
46
is smoothed out by a low-pass filter
47
. The output voltage signal from the filter
47
is supplied as a control voltage to the voltage-controlled oscillator circuit
43
. Shifts of the phases of the output signals FR and FV introduced at a startup or when a channel is switched are fed as the control voltage back to the voltage-controlled oscillator circuit
43
. As a result, the frequencies of the output signals FR and FV become coincident. That is, the PLL circuit locks up.
In the circuit shown in
FIG. 4
, the counters
42
and
44
do not start to count simultaneously. Therefore, the phase difference detected by the phase comparator circuit
45
does not agree with the actual phase difference between the output signals FR and FV. For example, it is assumed that the output signals FR and FV have periods of fR and fVl, respectively, in the initial state as illustrated in the timing chart of
FIG. 5
, and that the phase difference delivered from the phase comparator circuit
45
is &agr;
1
. If the output signal FV subsequently assumes a period of fV
2
, a phase difference &agr;
2
delivered from the phase comparator circuit
45
at the next phase comparison timing is given by
&agr;
2
=(
fR−&agr;
1
)−
fV
2
On the other hand, the actual phase difference &agr;
3
between the output signals FR and FV is given by
&agr;
3
=
fR−fV
2
In this way, the phase difference &agr;
2
produced from the phase comparator circuit
45
is not coincident with the actual phase difference &agr;
3
. Consequently, appropriate feedback control on the control voltage is not provided. This has prolonged the locking time.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a phase-locked loop circuit free of the foregoing problems.
In the present invention, a phase comparator circuit compares a first output signal from a first counter and a second output signal from a second counter in terms of phase. The first counter divides down the output frequency of a reference signal source. The second counter divides down the output frequency of a voltage-controlled oscillator (VCO) circuit. If the second output signal lags the first output signal in phase, the phase comparator circuit produces a first error signal having a pulse width corresponding to the lag of the phase. If the second output signal leads the first output signal in phase, the phase comparator circuit produces a second error signal having a pulse width corresponding to the lead of the phase. Either the first or second error signal is supplied as a control voltage to the VCO circuit via a charge pump circuit and via a low-pass filter circuit. During the interval in which the phase lags, the first counter is reset. During the interval in which the phase leads, the second counter is reset.
This synchronizes the starting points of the counting operations of the first and second counters. The phase difference detected by the phase comparator circuit is brought into coincidence with the actual phase difference between the first and second output signals. Hence, the locking time can be shortened.
Accordingly, the present invention provides a phase-locked loop circuit comprising: a reference signal source for producing an output signal of a reference frequency; a first counter for dividing down the reference frequency of the output signal from the reference signal source and producing a first output signal; a voltage-controlled oscillator circuit for producing an output signal having a frequency corresponding to a control voltage; a second counter for dividing down the output signal from said voltage-controlled oscillator circuit and producing a second output signal; a phase comparator circuit for comparing the first and second output signals from said first and second counters in phase, respectively, and producing a first error signal or a second error signal; a charge pump circuit driven by said first or second error signal from said phase comparator circuit; a low-pass filter for converting the output from said charge pump circuit into said control voltage and supplying it to said voltage-controlled oscillator circuit; and a control circuit. When the second output signal is lagging the first output signal in phase, the phase comparator circuit produces said first error signal having a pulse width corresponding to the lag of the phase. When the second output signal leads the first output signal, the phase comparator circuit produces said second error signal having a pulse width corresponding to the lead of the phase. When the phase is lagging, the control circuit resets the first counter. When the phase is leading, the control circuit resets the second counter.
Preferably, the control circuit resets the first or second counter, depending on whether the phase is lagging or leading, respectively, in response to the first or second error signal, respectively.
Other objects and features of the invention will appear in the course of the description thereof, which follows.
REFERENCES:
patent: 5461344 (1995-10-01), Andoh
patent: 6150891 (2000-11-01), Welland et al.
Grimm Siegfried H.
Schulte Roth & Zabel
Seiko Precision Inc.
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