Phase locked loop having adaptive jitter reduction

Details Phase locked loop having adaptive jitter reduction Phase locked loop having adaptive jitter reduction

1996-11-15

1998-10-27

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

327156, 331 17, H03L 706

Patent

active

058282556

ABSTRACT:
Jitter is controlled in a phase locked loop (PLL) adaptively and continuously in real time by a jitter control circuit. The jitter control circuit makes periodic PLL output jitter measurements and causes sequential measurements to be compared. The comparison provides an indication as to whether output jitter is being improved or degraded. Charge pump gains associated with internal parameters and external parameters that adversely affect output jitter are modified in response to the comparisons. If output jitter is adversely affected by an increment or decrement of one of the gain values, then the gain value is moved in the opposite direction. Output jitter is optimized for both gain values. Such optimization occurs during normal circuit operation and is continuous so as to adapt to changing conditions.

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IBM Technical Discloure Bulletin vol. 34 No. 4B Sep. 1991 pp. 468-473 Author: R. Coburn et al. "Analog PLL With Quick Phase Lock".

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