Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular frequency control means
Reexamination Certificate
1999-06-14
2001-01-30
Mis, David (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Particular frequency control means
C331S016000, C331S025000, C331S057000, C331S078000, C327S156000
Reexamination Certificate
active
06181213
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a phase-locked loop, and more particularly, to a phase-locked loop that utilizes a multi-phase voltage controlled oscillator to achieve frequency expansion effect.
BACKGROUND OF THE INVENTION
In the clock synthesizer of a mainboard, a phase-locked loop is often utilized to perform data recovery. Moreover, some modifications are often made to a phase-locked loop so that it has frequency expansion capability for reducing electromagnetic interference (EMI). However, there is no simple way to achieve frequency expansion in conventional phase-locked loops.
FIG. 1
illustrates a conventional phase-locked loop comprising a divided-by-N counter
11
, a divided-by-M counter
12
, a phase frequency detector
13
, a charge pump
14
, a loop filter
15
, and a voltage controlled oscillator
16
.
The divided-by-N counter
11
outputs a clock signal with frequency 1/N that of its input clock signal (i.e. f
xtal
), which will be denoted by f
xtal
/N in the following.
FIG. 2
illustrates the cases that the frequency f
xtal
is reduced to ½ and ⅓ of its original frequency respectively. The divided-by-M counter
12
outputs a clock signal with frequency 1/M that of its input clock signal (i.e. f
vco
), which will be denoted by f
vco
/M in the following. The phase frequency detector
13
compares the signals f
xtal
/N and f
vco
/M, outputs signals which are determined by the frequency difference and phase difference of the two signals f
xtal
/N and f
vco
/M. As shown in FIG.
3
(
a
), when the phase of f
vco
/M lags behind that of f
xtal
/N (as denoted in the figure by dotted lines), the phase frequency detector
13
outputs an ‘up’ signal. On the other hand, as shown in FIG.
3
(
b
), when the phase of f
vco
/M is ahead of that of f
xtal
/N (as denoted in the figure by dotted lines), the phase frequency detector
13
outputs an ‘dn’ signal. Referring to
FIG. 4
, the charge pump
14
and the loop filter
15
cooperatively convert the ‘up’ and ‘dn’ signals outputted from the phase frequency detector
13
into a voltage signal Vc. When the phase frequency detector
13
outputs an ‘up’ signal, the output voltage Vc of the loop filter
15
is increased. On the other hand, when the phase frequency detector
13
outputs an ‘dn’ signal, the output voltage Vc of the loop filter
15
is decreased. The voltage controlled oscillator
16
outputs a clock signal with frequency f
vco
determined by the output voltage Vc of the loop filter
15
. The frequency f
vco
increases as voltage Vc increases, and decreases as voltage Vc decreases.
As describe above, when the phase-locked loop is in a phase-locked state, the phase of f
xtal
/N is in alignment with that of f
vco
/M and the frequencies of these two clock signals are the same, as shown in FIG.
5
. In other words, f
vco
=(M/N)×f
xtal
. It can be seen from this equation that the f
vco
can be determined by M and N.
The concept of frequency expansion is described in the following. Assume that clock signals with some fixed frequency is desired, then clock signals with frequency varies in a predetermined frequency range centering at that frequency is generated. For example, frequency may vary linearly and periodically in a predetermined frequency range. Referring to
FIG. 1
, the frequency f
vco
can be made to vary linearly and periodically by making Vc vary linearly and periodically, which can be achieved by making the ‘up’ and ‘dn’ signals vary alternately and periodically. Moreover, the ‘up’ and ‘dn’ signals may be made to vary alternately and periodically by adjusting the values of M and/or N. As shown in
FIG. 5
, while the phase-locked loop
1
is in a phase-locked state, the phase of f
xtal
/N is in alignment with that of f
vco
/M and there is no ‘up’ or ‘dn’ signal generated. Referring to
FIG. 6
, when the value of M is suddenly changed to (M+&Dgr;M) or (M−&Dgr;M), the ‘up’ and ‘dn’ signals are alternately generated. Similarly, when the value of N is suddenly changed to (N+&Dgr;N) or (N−&Dgr;N), the up’ and ‘dn’ signals are alternately generated as well.
As described above, controlling the value of M (or N) results in the ‘up’ and ‘dn’ signals being generated alternately. This, in turn, leads to Vc varying linearly and periodically. Consequently, the value of f
vco
varies linearly and periodically.
FIG. 7
shows the variation of f
vco
when M varies through a series of increments (&Dgr;M) and then a series of decrements (−&Dgr;M) From the figure, it can be seen that f
vco
varies linearly and periodically in a predetermined frequency range centering at the frequency f.
From the above description, it can be seen that a phase-locked loop can achieve the effect of frequency expansion by controlling the values of M and N. However, controlling M and N is not easy and may require a complicated circuit.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a simple phase-locked loop having frequency expansion capability.
The present invention is primarily characterized in that a multi-phase voltage controlled oscillator instead of a conventional voltage controlled oscillator is used in a phase-locked loop and a switching unit is used to select the output signal from the multi-phase voltage controlled oscillator. The switching time of the switching unit is controlled by a clock counter.
To achieve the aforementioned object, a phase-locked loop having a multi-phase voltage controlled oscillator is provided. It includes a divided-by-N counter, a divided-by-M counter, a phase frequency detector, a charge pump, a loop filter, a multi-phase voltage controlled oscillator, a switching unit, and a clock counter wherein, the divided-by-N counter outputs a clock signal with frequency 1/N of its input signal. The divided-by-M counter outputs a clock signal with frequency 1/M of its input signal. The phase frequency detector receives the output signal from the divided-by-N counter and the output signal from the divided-by-M counter, outputs a control signal that is determined by the phase difference and frequency difference between the two received signals. The charge pump receives the control signal outputted from the phase frequency detector. The loop filter is coupled to and cooperates with the charge pump to generate a voltage signal. The multi-phase voltage controlled oscillator receives the voltage signal generated by the loop filter and outputs a plurality of clock signals of the same frequency and different phases, wherein one of the clock signals is used as the output clock signal of the phase-locked loop. The switching unit is connected between the divided-by-M counter and the multi-phase voltage controlled oscillator for selecting a clock signal among the output clock signals from the multi-phase voltage controlled oscillator as the input signal for the divided-by-M counter. The clock counter generates a control signal for controlling the switching time of the switching unit.
From the description in the preceding paragraph, it can be seen that a multi-phase voltage controlled oscillator instead of a conventional voltage controlled oscillator is used in accordance with the present invention. A switching unit is incorporated to select an output signal from the multi-phase voltage controlled oscillator, whose switching time is controlled by a clock counter. Consequently, the frequency expansion effect of the phase-locked loop in accordance with the invention can be achieved by merely a simple modification made to a conventional phase-locked loop.
REFERENCES:
patent: 4035833 (1977-07-01), Shepard
patent: 5889436 (1999-03-01), Yeung et al.
patent: 5994933 (1999-11-01), Yamanaka et al.
Bacon & Thomas PLLC
Mis David
REALTEK Semiconductor Corp.
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