Phase locked loop having a fast lock current reduction and clamp

Details Phase locked loop having a fast lock current reduction and clamp Phase locked loop having a fast lock current reduction and clamp

1988-02-03

1989-12-26

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

331 17, 328133, 328155, H03L 710

Patent

active

048900729

ABSTRACT:
A circuit for use in a phase locked loop (PLL) which is responsive to the PLL being out of lock for providing fast lock current to drive the VCO of the PLL in the direction to acquire lock. The circuit includes a pair of controlled current sources responsive to selective control signals for either sourcing or sinking fast lock current at the output of the circuit that are utilized to produce an error control voltage at the loop filter to drive the VCO accordingly while a reducing circuit is responsive to the control voltage reaching a predetermined value as the VCO is driven toward one end or the other of its range for clamping the control voltage while reducing the fast lock current to a reduced value thereby limiting excessive charge build-up on the loop filter capacitor of the PLL. Thus, the circuit permits the VCO to acquire fast lock up by providing fast lock current thereto while clamping the range of the VCO and reducing the fast lock current as the VCO approaches either end of its range. Upon acquiring lock up, the controlled current sources are disabled.

REFERENCES:
patent: 4377728 (1983-03-01), Hilbert
patent: 4517529 (1985-05-01), Lindstedt et al.
patent: 4562410 (1985-12-01), O'Rourke
patent: 4596963 (1986-06-01), Lawton et al.

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