Phase-locked loop frequency synthesizer

Details Phase-locked loop frequency synthesizer Phase-locked loop frequency synthesizer

1980-07-14

1982-11-23

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 25, 307271, 328 15, H03L 718

Patent

active

043607888

ABSTRACT:
A programmable divide-by-N phase-locked loop having a pulse incrementor circuit and a single sideband mixer circuit embedded in the loop feedback path is disclosed. In each disclosed arrangement, one input port of the single sideband mixer receives the signals supplied by the phase-locked loop voltage controlled oscillator and, depending upon whether the mixer employed is configured for supplying an upper sideband signal or a lower sideband signal, either increases or decreases the frequency of the phase-locked loop feedback signal by a factor f.sub.s, where f.sub.s is the frequency of a control signal applied to the second input port of the signal sideband mixer. The pulse incrementor circuit receives the signal supplied by the single sideband mixer and, depending on whether the pulse incrementor is configured for deleting signal pulses or adding signal pulses, either decreases or increases the average frequency of the signals supplied to the phase-locked loop programmable divider by a factor f.sub.d, where f.sub.d is the frequency of a control signal applied to the pulse incrementor. Since the phase-locked loop synchronizes or locks when the phase of the signal supplied by the programmable divider is equal to the phase of a reference frequency f.sub.r, which is supplied to the phase-locked loop phase detector, the arrangement causes the phase-locked loop voltage controlled oscillator to supply a signal at a frequency of Nf.sub.r .+-.f.sub.d .+-.f.sub.s, where N is the selected divisor of the phase-locked loop programmable divider and the operations of addition and subtraction are determined by the type of single sideband mixer and pulse incrementor utilized. To suppress spurious output signals, both control frequencies f.sub.d and f.sub.s are maintained substantially above the phase-locked loop cutoff frequency. Separate pulse incrementor circuits for pulse deletion and pulse addition are disclosed, along with a combined pulse deletor programmable divider which utilizes variable modulus prescaling techniques.

REFERENCES:
patent: 3777276 (1973-12-01), Klein
patent: 3875524 (1975-04-01), Harzer et al.
patent: 4206425 (1980-06-01), Nossen
patent: 4225828 (1980-09-01), Watanabe et al.
"Phase-Locked Loop Data Book"; second edition, Aug. 1973; Motorola Inc., 1973; pp. 1-13.
Gillette, "The Digitphase Synthesizer" Frequency Technology, Aug. 1969, pp. 25-29.
Telewski et al. "Delay Lines Give RF Generator Spectral Purity, Programmability" Electronics, Aug. 1980, pp. 133-142.

Affiliated with

Also associated with

Rating

Phase-locked loop frequency synthesizer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Phase-locked loop frequency synthesizer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase-locked loop frequency synthesizer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1881136