Phase locked loop frequency modulator using fractional division

Details Phase locked loop frequency modulator using fractional division Phase locked loop frequency modulator using fractional division

1993-06-22

1994-08-09

Grimm, Siegfried H.

Modulators

Frequency modulator

Including stabilization or alternatively distortion, noise...

375 44, 455 42, 455 76, 455113, H03C 309

Patent

active

053370244

ABSTRACT:
A frequency modulation circuit includes a phase-locked loop having a reference frequency input and a controlled frequency output. The phase-locked loop has a phase detector, a filter and a voltage-controlled oscillator and, in a feedback path between the output and the phase detector, a frequency divider. Also included is a converter converting an input signal to a digital modulation signal M, and an adder inverting the most significant bit of the digital modulation signal and adding it to a digital word representing a selected frequency. The frequency divider divides a fractional number (N.F).+-.M, where N is an integer, F is a fraction and M is the digital value of modulation data. This configuration is advantageous because data can be taken directly from the analog-to-digital output to the adder with no data translation, the modulation signal M could also be provided from a processor data bus, the peak deviation is selectable, and no carrier offset results from injecting the modulation signal into the phase-locked loop.

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