Phase locked loop for recovering data bit timing

Details Phase locked loop for recovering data bit timing Phase locked loop for recovering data bit timing

1980-07-10

1982-06-01

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 17, 331 23, 331 27, H03L 708

Patent

active

043330606

ABSTRACT:
Three sample and hold circuits (26, 30 and 34) sample a received pulse amplitude modulated signal at twice the data bit frequency or timing of the received signal. The clock to the sample and hold circuits is timed so that three consecutive samples, two mid-bit samples and a transition sample are held in the circuits (26, 30 and 34) once every two sample periods. The mid-bit samples are added together by an adder (32) and divided by two in a divider (38) to provide an average. The transition sample is subtracted from this average in a subtractor (36) to produce an error signal. The error signal is normalized in a multiplier (44) using the reciprocal of the difference in magnitude between the two mid-bit samples to produce a normalized signal. A clock signal is generated by a voltage controlled oscillator (52) in response to the normalized signal at twice the bit frequency or bit timing and in synchronism therewith.

REFERENCES:
patent: 3691474 (1972-09-01), Calaway
patent: 3973212 (1976-08-01), Walloch
patent: 4128811 (1978-12-01), Englund, Jr.
patent: 4219784 (1980-08-01), Detering

Affiliated with

Also associated with

Rating

Phase locked loop for recovering data bit timing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Phase locked loop for recovering data bit timing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Phase locked loop for recovering data bit timing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1851571