Phase locked loop for recovering a clock signal from a data...

Details Phase locked loop for recovering a clock signal from a data... Phase locked loop for recovering a clock signal from a data...

2003-06-06

2004-09-14

Kinkead, Arnold (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

C331S025000, C331S010000, C327S156000, C327S158000, C327S159000, C375S376000

Reexamination Certificate

active

06791420

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a phase locked loop for recovering a clock signal from a data signal, having a delay locked loop with a phase detector with a first input that is coupled to a connection for supplying a signal that can be derived from the clock signal, and with a second input that is coupled to a connection for supplying the data signal, with an integrator that is connected to one output of the phase detector, and with a delay element that is connected by a control input to one output of the integrator and that is connected on the output side to one of the two inputs of the phase detector, a loop filter that is connected to the output of the integrator, and a voltage controlled oscillator that is connected on the input side to one output of the loop filter and at whose output the clock signal can be tapped off.
Recovery of a clock signal from a received data signal, for example, a binary signal with a random sequence of zeros and ones, is a central problem in data technology and telecommunications technology.
One possible solution approach is to use a phase locked loop with a digital phase detector, which produces an actuating signal for a local oscillator. In such a case, the phase angle of the data signal is compared with the clock phase of the clock signal in a digital phase detector of this type in each case with respect to the flank changes in the data signal, that is to say, the changes from logic 0 to logic 1 and vice-versa The phase detector in such a case produces at its output the information “clock too early”, “clock too late”, or “clock correct or phase unknown”. This signal information is used for keying a frequency of an output signal of a local voltage controlled oscillator (VCO), and, thus, for following the phase angle of the data signal. This principle is specified, by way of example, in the article “Clock Recovery from Random Binary Signals”, J. D. H. Alexander, Electronics Letters Vol. 11, No. 22 (1975), pages 541 to 542 as well as in the article “Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s”, A. Pottbäkker, U. Langmann, IEEE Journal of Solid-State Circuits, Vol. 27, No. 12 (1992), pages 1747 to 1751.
The use of a digital phase detector in a phase locked loop PLL for obtaining a clock signal from a data signal can be implemented quite easily in terms of the circuitry. The digital or nonlinear method of operation of the phase detector is, however, a disadvantage for the transmission system in comparison to a linear method of operation because, in the event of any phase error, only its mathematical sign is known, but not the magnitude of the discrepancy. In consequence, it is not possible to specify a linear transfer function for the system or a modulation bandwidth for the phase modulation. However, because the transmission of data over long distances is a frequent objective in telecommunications technology, in the process of which a large number of signal regenerators have to be connected in series, it is desirable for the circuits used for clock recovery to be linear and to have a well-defined modulation bandwidth.
German Published, Non-Prosecuted Patent Application DE 198 42 711 A1, corresponding to U.S. Pat. No. 6,433,599 to Friedrich et al., discloses a circuit for data signal recovery and for clock signal regeneration in which, in addition to the PLL for clock recovery with a digital phase detector, a second PLL is provided and has a linear, analog phase detector, is connected downstream from the first PLL, and produces an output clock signal from the clock that is produced in the first stage. However, such a circuit requires a second voltage-controlled oscillator with the additional complexity that is associated therewith.
The article “A 155-MHz Clock Recovery Delay- and Phase-Locked Loop”, T. H. Lee, J. F. Bulzacchelli, IEEE Journal of Solid-State Circuits, Vol. SC-27, December 1992, pages 1736 to 1746, discloses a circuit of this generic type in which a delay locked loop DLL is combined with a phase locked loop PLL, connected in parallel. It is, thus, possible to achieve very fast clock signal recovery with high performance and good jitter characteristics. The phase detector that is used may, in such a case, assume two or more output values, for example, five output values, which are integrated in a loop integrator to form a triangular waveform signal.
The loop filter in the control loop that is described in the article has a pure integrator without any proportional component, see
FIG. 9
, with the function H
f
=K
D
/s. The output of this loop filter is connected to a voltage-controlled oscillator VCO. This VCO must be a high-precision crystal oscillator (VCXO), whose frequency differs only insignificantly from the data rate. Any difference between the oscillator frequency and the data rate of the data signal must be compensated for by a steady-state actuating value for the loop filter, which also controls the controllable delay element. This restricts the phase control range of the delay loop, as is explained in the Chapter “C. Acquisition Behavior of the D/PLL”.
The described D/PLL is configured by the two poles of the phase transfer function (jitter transfer function) H(s), see Chapter B, which can be adjusted by the DLL parameters K
D
and K
&PHgr;
as well as the PLL parameter K
0
. However, linear components, in particular, a linear phase detector with a defined detector constant K
D
, are required for correct configuration of this linear function. This phase detector must be able to make a quantitative statement relating to the phase error, in addition to a qualitative statement.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a phase locked loop for recovering a clock signal from a data signal that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that makes possible a linear phase locked loop whose design has been simplified further.
A clock signal normally has a predefined known sequence of binary coded series of zeros and ones, which, normally, also alternate.
In contrast, a data signal carries coded information that, for example, is not known a priori to a receiver, such as speech data, text data, graphics data or other data. Thus, even if the use of a scrambler makes it possible to achieve an equal probability of the occurrence of zeros and ones when averaged over a lengthy time period, it is not necessary to know, for example, at the receiver the clock information on which the data signal is based. In consequence, the recovery of a clock signal from a data signal is of major importance in information and communications technology.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a phase locked loop for recovering a clock signal from a data signal, including a delay locked loop having a connection for supplying a signal to be derived from the clock signal, a connection for supplying the data signal, a nonlinear phase detector having a first input coupled to the connection for supplying the signal, a second input coupled to the connection for supplying the data signal, and at least one output, the nonlinear phase detector producing, at the at least one output, one of a signal able to assume one of only three states including a first state in which a phase of the clock signal leads a phase of the data signal, a second state in which the phase of the clock signal lags the phase of the data signal, and a third state in which a phase angle of the clock signal and a phase angle of the data signal one of match and are instantaneously unknown, and a binary signal, an integrator having an output and an input connected to the at least one output of the phase detector, and a delay element having a control input connected to the output of the integrator and an output connected to one of the first and second inputs of the phase detector, a loop filter having an output, an input connected to the output of t

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