Phase-locked loop for PCM transmission systems

Details Phase-locked loop for PCM transmission systems Phase-locked loop for PCM transmission systems

1979-02-02

1980-12-09

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

331 8, 331 27, H03L 708

Patent

active

042387400

ABSTRACT:
A phase-locked loop for PCM transmission systems has a phase comparator (20) which provides continuous regulation of the loop oscillator (30). When a PCM pulse signal is present, the phase comparator selectively compares the PCM and oscillator clock signal and generates an error signal which synchronizes the oscillator to the PCM frequency. During the absence of a PCM pulse, the phase comparator provides a high impedance output and oscillator synchronization is maintained by a loop filter (23). In the disclosed embodiment, the phase comparator is a dual section tristate gate (300).

REFERENCES:
patent: 3351868 (1967-11-01), Farrow
patent: 3701039 (1972-10-01), Lang et al.
patent: 3983506 (1976-09-01), Rettinger, Jr. et al.
Cordell et al., "A Highly Stable VCO for Application in Monolithic Phase-Locked Loops", IEEE Journal of Solid State Circuits, vol. SC-10, No. 6, Dec. 1975, pp. 480-485.
D'Altroy, "Switching to Solid State Relays", Bell Laboratories Record, Feb. 1978, pp. 30-37.

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