Phase locked loop for MPEG system

Details Phase locked loop for MPEG system Phase locked loop for MPEG system

1996-08-09

1999-11-30

Follansbee, John A.

Television

Synchronization

348516, 348521, 348536, 331 1R, 4551803, H04N 504, H03L 700

Patent

active

059951567

ABSTRACT:
A phase locked loop for synchronizing decoding clocks with encoding clocks in a Moving Picture Experts Group (MPEG) system. The phase-locked loop circuit includes a voltage controlled oscillator for converting a decoding clock into an encoding clock, a register unit for storing multiplexing program clock reference signals, each input with a desired number of bits, a counter being initialized by a first program clock reference signal output from the register unit, thereby generating a local program clock reference signal, and a phase error control unit for combinationally operating the program clock reference signal stored in the register unit and the local program clock reference signal, thereby generating a phase error signal for controlling the voltage controlled oscillator.

REFERENCES:
patent: 4305045 (1981-12-01), Metz et al.
patent: 4972442 (1990-11-01), Steierman
patent: 5008749 (1991-04-01), Ruckert
patent: 5467342 (1995-11-01), Logston et al.
patent: 5473385 (1995-12-01), Leske
patent: 5528183 (1996-06-01), Maturi et al.
patent: 5588025 (1996-12-01), Strolle et al.
patent: 5768326 (1998-06-01), Koshiro et al.

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