Phase locked loop for deriving clock signal from aperiodic data

Details Phase locked loop for deriving clock signal from aperiodic data Phase locked loop for deriving clock signal from aperiodic data

1978-11-24

1980-09-09

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

328134, 328155, 331 27, H03B 304

Patent

active

042220130

ABSTRACT:
A phase locked loop circuit (100) for generating a periodic clock signal from a controlled oscillator circuit (130) in phase coincidence with a synchronous aperiodic data input signal is disclosed. A pulse of the data signal and a corresponding pulse of the clock signal are applied to a bistable circuit (FF1) having an output signal indicating which of the pulses occurs first in time. The pulses are further applied through delay circuitry (DLY1, DLY2) to another bistable circuit (FF2) having an output signal indicative of the magnitude of phase difference between the pulses. The output signals of the bistable circuits (FF1, FF2) are applied to a multilevel driver circuit (140) which generates an error correction signal pulse defining magnitude and direction of a correction signal to be applied to the oscillator circuit (130).

REFERENCES:
patent: 3544907 (1970-12-01), Bleickard
patent: 3599110 (1971-08-01), Gindi
patent: 3714589 (1973-01-01), Lewis
patent: 3983498 (1976-09-01), Malek
patent: 3986125 (1976-10-01), Eibner
patent: 4055814 (1977-10-01), Abraham et al.
patent: 4085288 (1978-04-01), Viswanathan

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