Phase locked loop for controlling recordable optical disk drive

Details Phase locked loop for controlling recordable optical disk drive Phase locked loop for controlling recordable optical disk drive

2002-11-18

2004-06-22

Huber, Paul W. (Department: 2653)

Dynamic information storage or retrieval

Control of storage or retrieval operation by a control...

Control of information signal processing channel

C369S053310

Reexamination Certificate

active

06754147

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a phase locked loop (PLL), and more specifically, to a method for using a PLL in a recordable optical disk drive to perform phase shift detection while recording to a recordable disk.
2. Description of the Prior Art
A phase locked loop is used for frequency control. Please refer to FIG.
1
.
FIG. 9
is a block diagram of a phase locked loop (PLL)
10
for controlling a recordable optical disk drive according to the prior art. The PLL
10
generates a clock signal CLK in response to a wobble signal WOBBLE. The wobble signal WOBBLE is extracted from the wobble tracks of a recordable optical disk, as shown in
FIG. 2
, and contains address information of the wobble tracks. The clock signal CLK is used to control the writing path of the recordable drive and is the reference for the recording clock. A period of the wobble signal WOBBLE corresponds to 186 periods of the clock signal CLK for a DVD-R/RW specification, and a period of the wobble signal WOBBLE corresponds to 32 periods of the clock signal CLK in a DVD+R/RW specification. To ensure synchronized writing data to the correct track at the right time, the PLL synchronizes the clock signal CLK with the wobble signal WOBBLE.
The PLL
10
contains a phase detector
12
, which is used for comparing phases of the wobble signal WOBBLE and the clock signal CLK. Based on a phase difference between the wobble signal WOBBLE and the clock signal CLK, the phase detector
12
then outputs either an up signal UP or a down signal DN to a charge pump circuit
14
. Based on receipt of either the up signal UP or the down signal DN, the charge pump circuit
14
sends or receives a control current to a loop filter
16
. Next, a control voltage is outputted from the loop filter
16
and fed into a voltage controlled oscillator (VCO)
18
. The VCO
18
generates the clock signal CLK with an output frequency based on the control voltage. An optional frequency divider
20
can be used for dividing the frequency of the clock signal CLK, and finally the clock signal CLK is fed back into the phase detector
12
. Together, the phase detector
12
, the charge pump circuit
14
, the loop filter
16
, the VCO
18
, and the frequency divider
20
form the PLL
10
, which is a feedback loop.
However, sometimes the PLL
10
cannot synchronize the phase of the clock signal CLK with the phase of the wobble signal WOBBLE due to a phase shift phenomenon. The phase shift phenomenon occurs due to a limit of the conventional phase detector
12
. Please refer to FIG.
3
A through FIG.
3
E. FIG.
3
A through
FIG. 3E
are phase shift diagrams illustrating operation of the phase detector
12
under various circumstances. Based on an input phase shift &thgr;
e
, the phase detector
12
generates an output u
d
for correcting the phase shift &thgr;
e
. The output u
d
is shown in
FIG.1
as either being the up signal UP or the down signal DN, and is used to synchronize the clock signal CLK with the wobble signal WOBBLE. As long as the phase shift &thgr;
e
is within a locking range a &Dgr;w
L
of the phase detector
12
, the phase detector
12
is able to synchronize the clock signal CLK with the wobble signal WOBBLE. The locking range &Dgr;w
L
of the phase detector
12
is usually equal to a phase difference of plus or minus half a period of the wobble signal WOBBLE. As will be shown shortly, a problem occurs when the phase shift &thgr;
e
falls outside of the locking range &Dgr;w
L
of the phase detector
12
.
In
FIG. 3A
, point
30
represents the output function of the phase detector
12
. Because the phase shift &thgr;
e
has a value of 0, no action is needed by the phase
12
to correct the phase shift &thgr;
e
, and the phase detector
12
outputs a corresponding output u
d
also having a value of 0. When the phase shift &thgr;
e
does not have a value of 0, the output function of the phase detector moves along the diagonal lines shown in FIG.
3
A. When the phase shift &thgr;
e
becomes larger than the locking range &Dgr;w
L
, the output function will follow the diagonal lines shown outside of the locking range &Dgr;w
L
. Point
30
is located at a crossing point, which is where the diagonal lines of the output function pass through the axis representing the phase shift &thgr;
e
, and each crossing point has an output u
d
of 0.
The job of the phase detector
12
is to correct the phase shift &thgr;
e
such that the phase shift &thgr;
e
always locks onto the point
30
shown in
FIG. 3A
since this is the only way the phase shift &thgr;
e
will have a value of 0. As long as the phase shift &thgr;
e
is within the locking range &Dgr;w
L
, the phase detector
12
will track and lock the phase shift &thgr;
e
to have a value of 0. Notice that just because the output u
d
d
has a value of 0, it does not necessarily imply that the phase shift &thgr;
e
has a value of 0.
In
FIG. 3B
, point
32
shows a case in which the inputted phase shift &thgr;
e
has a value greater than 0, but is still within the locking range &Dgr;w
L
. Since point
32
is not located on a crossing point, the phase detector
12
will generate the output u
d
in order to lock the phase shift &thgr;
e
onto the nearest crossing point.
FIG. 3C
shows the result of this, and point
34
shows the locking of the phase shift &thgr;
e
onto the crossing point in the middle of the locking range &Dgr;w
L
. Since point
32
in
FIG. 3B
was within the locking range &Dgr;w
L
, point
34
in
FIG. 3C
is locked to the crossing point in the locking range &Dgr;w
L
, and not locked to one of the crossing points outside of the locking range &Dgr;w
L
.
FIG.
3
D and
FIG. 3E
show the problems that arise when the phase shift &thgr;
e
is not in the locking range &Dgr;w
L
. In
FIG. 3D
, point
36
shows a case in which the inputted phase shift &thgr;
e
has a value greater than 0, and is not within the locking range &Dgr;w
L
. Since point
36
is not located on a crossing point, the phase detector
12
will generate the output u
d
in order to lock the phase shift &thgr;
e
onto the nearest crossing point.
FIG. 3E
shows the result of this, and point
38
shows the locking of the phase shift &thgr;
e
onto the crossing point that is immediately to the right of the locking range &Dgr;w
L
. Since point
36
in
FIG. 3D
was to the right of the locking range &Dgr;w
L
, point
38
in
FIG. 3E
is locked to the crossing point to the right of the locking range &Dgr;w
L
, and not the crossing points in the middle of the locking range &Dgr;w
L
.
Please refer to FIG.
4
A through FIG.
4
E. FIG.
4
A through
FIG. 4E
are circular phase shift diagrams analogous to FIG.
3
A through
FIG. 3E
, respectively. The circular phase diagrams of FIG.
4
A through
FIG. 4E
are another way of representing the information in the phase diagrams of FIG.
3
A through
FIG. 3E
, and are shown for convenience. In
FIG. 4A
to
FIG. 4E
, the dotted circles are used to represent a continuous, loop characteristic of the phase shift &thgr;
e
. The horizontal line running through the dotted circle represents the locking range &Dgr;w
L
. The right side of the horizontal line is labeled “0”, and represents a phase shift &thgr;
e
of 0+n * &Dgr;w
L
, where n is an integer such as
1
,
2
,
3
, etc. The left side of the horizontal line is labeled “±½ &Dgr;w
L
”, and represents, a phase shift &thgr;
e
of ½ &Dgr;w
L
±m * &Dgr;w
L
, where m is also an integer such as
1
,
2
,
3
, etc.
In
FIG. 4A
, point
40
represents the output function of the phase detector
12
. Because the phase shift &thgr;
e
has a value of 0, no action is needed by the phase
12
to correct the phase shift &thgr;
e
, and the phase detector
12
outputs a corresponding output u
d
also having a value of 0. Please notice that just because the output u
d
has a value of 0, it does not necessarily imply that the phase shift &thgr;
e
has a value of 0. The phase shift &thgr;
e
could also have a value of 0+n * &Dgr;w
L
.
In
FIG. 4B
, point

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