Phase-locked loop for clock recovery

Details Phase-locked loop for clock recovery Phase-locked loop for clock recovery

1996-05-30

1998-06-02

Callahan, Timothy P.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 25, 331 18, 331 23, 327156, 327263, 327264, H03D 324

Patent

active

057606536

ABSTRACT:
A PLL circuit includes a sampling pulse generator and a loop circuit using a sample and hold circuit as a phase detector. The sampling pulse generator generates a sampling pulse signal at each level transition of an NRZ input signal. The sample and hold circuit samples a clock signal and hold a voltage signal corresponding to a voltage of the clock signal according to the sampling pulse signal. A voltage-controlled oscillator included in the loop circuit generates the clock signal whose frequency is controlled based on tho voltage signal received from the sample and hold circuit through a loop filter. The voltage signal remains at an appropriate level even when the NRZ input signal remains at the same level for a relatively long time. The sampling pulse generator includes a delay circuit for delaying the NRZ input signal and an exclusive-OR circuit receiving the NRZ input signal and the delayed signal.

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Zhi-Gong Wang, et al., 7.5 GB/s Monolithically Integrated Clock Recovery Circuit Using PLL and 0.3-.mu.m Gate Length Quantum Well HEMT's, IEEE Journal of Solid-State Circuits, vol. 29, No. 8, pp. 995-997, Aug. 1994.

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