Phase locked loop for clock extraction in gigabit rate data comm

Details Phase locked loop for clock extraction in gigabit rate data comm Phase locked loop for clock extraction in gigabit rate data comm

1988-11-18

1990-05-15

Safourek, Benedict V.

Pulse or digital communications

Spread spectrum

Direct sequence

3701051, 328155, H04L 733

Patent

active

049264478

ABSTRACT:
A family of Phase Locked Loop circuits and methods for extraction of a clock signal from a digital data stream, for example as received by a data communication link receiver is taught. The circuits of this invention are particularly advantageous in gigabit rate links where the propagation delay of digital circuits is comparable to the duration of a bit time interval and therefore careful matching of clock extracting and data sampling circuit topology is required. In certain embodiments, a frequency detector is included making the structure suitable for use in situations where there is a large fractional difference between the incoming data rate and the free running frequency of the receiver VCO. Such is the case when both the incoming data rate and the receiver VCO frequency are not controlled by a precision element such as a crystal or a Surface Acoustic Wave device.

REFERENCES:
patent: 4280099 (1981-07-01), Rottlingourd
patent: 4371974 (1983-02-01), Dugan
patent: 4400667 (1983-08-01), Belkin
patent: 4633488 (1986-12-01), Shaw
patent: 4743857 (1988-05-01), Childers
patent: 4782484 (1988-12-01), Limb
"Clock Recovery for A 5 Gbit/s Fibre-Optic System" in Electronic Letters, 24th Jun., (1982), vol. 18, No. 13, pp. 547-548.
"Clock Recovery from Random Binary Signals" in Electronic Letters 30th Oct., (1975), vol. 11, No. 22, pp. 541-542.
"A Self Correcting Clock Recovery Circuit" by Charles R. Hogge, Jr., in IEEE Transactions on Electron Devices, vol. ED-32, No. 12, Dec., 1975, pp. 2704-2706.

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